Analog switch circuit having output offset compensation circuit

Details Analog switch circuit having output offset compensation circuit Analog switch circuit having output offset compensation circuit

1983-11-17

1986-07-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307579, 307585, H03K 1716, H03K 17687

Patent

active

045995222

ABSTRACT:
An analog switch circuit which is provided with a transmission gate consisting of a first n channel MOS transistor and a first p channel MOS transistor, which transistors are connected in parallel, wherein the output terminal of said transmission gate is connected to a second n channel MOS transistor and a second p channel MOS transistor, which transistors are supplied with an output voltage Vout from the transmission gate, and wherein mirror capacitances C.sub.mP12, C.sub.mP13, C.sub.mN12, C.sub.mN13 are provided at the output terminal of the transmission gate to offset a difference between the mirror capacitance C.sub.mN11 of the first n channel MOS transistor and the mirror capacitance C.sub.mP11 of the first p channel MOS transistor.

REFERENCES:
patent: 4075509 (1978-02-01), Redfern
patent: 4198580 (1980-04-01), Culmer
patent: 4393318 (1983-07-01), Takahashi et al.
patent: 4467227 (1984-08-01), Lewyn et al.
patent: 4473761 (1984-09-01), Peterson
patent: 4511814 (1985-04-01), Matsuo et al.

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