Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices
Reexamination Certificate
2000-10-26
2003-05-20
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
With particular solid state devices
C327S534000, C257S370000
Reexamination Certificate
active
06567024
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog switch. The present invention also relates to an A/D converter with the analog switch.
2. Description of the Related Art
A plurality of analog switches are employed, for example, in a sample and hold circuit. The sample and hold circuit having a plurality of analog switches are used in such a structure where the circuit is connected, for example, to a successive approximation type A/D converter.
The sample and hold circuit samples a predetermined one of a plurality of analog input signals, and holds the signal for a predetermined period, and supplies the A/D converter with the signal.
Particularly, the plurality of input signals are sent to a plurality of analog switches, respectively. One of the plurality of analog switches operates in a mode wherein an input signal passes through the analog switch, thereby the input signal is sent to the A/D converter.
When the analog switch is in such a mode, the analog switch is said to be in a selective mode. On the contrary, when the analog switch operates in a mode wherein one input signal does not passes through the analog switch, the analog switch is said to be in a non-selective mode.
Likewise the structure of automobiles, in a structure where a source voltage largely varies and an input signal has substantially the same level as that of the source voltage, if the level of the input signal is larger than the level of the source voltage, the input signal may partially pass through the analog switch being in a non-selective mode. An injection current which may be caused by such an input signal partially passing through the switch has an effect on an input signal to be sent to the A/D converter, i.e., on an input voltage of the A/D converter.
In order to prevent occurrence of the injection current, an analog switch generally has two transfer gates in two stages of an input stage and an output stage. In addition, there is included a transistor switch for controlling a connection point of the transfer gates to be grounded when the analog switch is in a non-selective mode. Further, the potential of the back gate (substrate electrode) of an N-channel MOS transistor, included in one transfer gate as an input stage, is set to the same as that of an input signal.
Having thus formed the analog switch, the analog switch has the large circuitry structure for preventing the occurrence of an injection current.
FIG. 4
is a circuitry diagram showing a general analog switch wherein an injection current is prevented from occurring.
As illustrated in
FIG. 4
, the analog switch comprises transfer gates
100
and
200
, inverters
4
,
5
and
600
, and a transistor (N-channel MOS transistor) N
31
.
The transfer gates
100
and
200
is cascade-connected with each other between an input terminal TI and an output terminal TO. A connection point of the transfer gates
100
and
200
is denoted by X
1
.
The transfer gate
100
includes transistors (N-channel MOS transistors) N
101
, N
102
, N
103
, N
104
and transistors (P-channel MOS transistors) P
101
, P
102
and P
103
.
The sources of the transistors N
101
and P
101
are connected with each other, the sources of the N
102
and P
102
are connected with each other, and the sources of the N
103
and P
103
are connected with each other. The drains of the transistors N
101
and P
101
are connected with each other, the drains of the N
102
and P
102
are connected with each other, and the drains of the N
103
and P
103
are connected with each other.
The sources of the transistors N
101
and P
101
are connected to the input terminal TI, and the drains thereof are connected to the connection point X
1
. The source of the transistors N
102
and P
102
are connected to the source of the transistors N
103
and P
103
, and the drains thereof are connected to the input terminal TI. The sources of the transistors N
103
and P
103
are connected to the source of the transistors N
102
and P
102
, and the drains thereof are connected to the connection point X
1
.
The gates of the transistors N
101
, N
102
and N
103
are connected with each other, and receive a sampling control signal C. The gates of the transistors P
101
, P
102
and P
103
are connected with each other, and receive a sampling control signal CB.
Furthermore, the back gates of the transistors N
101
, N
102
, N
103
are connected to the sources of the transistors N
102
and P
102
(or the source of the transistors N
103
and P
103
). The back gates of the transistors P
101
, P
102
and P
103
are connected to the power supply.
The gate of the transistor N
104
is connected to the gates of the transistors P
101
, P
102
, P
103
, the source of the transistor N
104
is grounded, and the drain thereof is connected to the source of the transistors N
102
and P
102
(or the source of the transistors N
103
and P
103
).
The transfer gate
200
includes transistors (N-channel MOS transistors) N
201
, N
202
, N
203
, N
204
, and transistors (P-channel MOS transistors) P
201
, P
202
and P
203
.
The sources of the transistors N
201
and P
201
are connected with each other. The sources of the transistors N
202
and P
202
are connected with each other. The sources of the transistors N
203
and P
203
are connected with each other. The drains of the transistors N
201
and P
201
are connected with each other. The drains of the transistors N
202
and P
202
are connected with each other. The drains of the transistors N
203
and P
203
are connected with each other.
The sources of the transistors N
201
and P
201
are connected to the connection point X
1
, whereas the drains thereof are connected to the output terminal TO. The sources of the transistors N
202
and P
202
are connected to the sources of the transistors N
203
and P
203
, while the drains thereof are connected to the connection point X
1
. The sources of the transistors N
203
and P
203
are connected to the sources of the transistors N
202
and P
202
, while the drains thereof are connected to the output terminal TO.
The gates of the transistors N
201
, N
202
and N
203
are connected with each other, and receive a sampling control signal C. The gates of the transistors P
201
, P
202
and P
203
are connected with each other, and receive a sampling control signal CB.
The back gates of the transistors N
201
, N
202
and N
203
are connected to the sources of the transistors N
202
and P
202
(or the sources of the transistors N
203
and P
203
). The back gates of the transistors P
201
, P
202
and P
203
are connected to the power source.
The gate of the transistor N
204
is connected to the gates of the transistors P
201
, P
202
and P
203
, the source of the transistor N
204
is grounded, and the drain thereof is connected to the sources of the transistors N
202
and P
202
(or the sources of the transistors N
203
and P
203
).
The inverter
4
supplies the gate of the transistor N
31
with a pull-down control signal PD for controlling the connection of the connection point X
1
and the ground, in accordance with a select signal S. The inverter
4
includes a transistor (N-channel MOS transistor) N
41
and a transistor (P-channel MOS transistor) P
41
.
The gates of the transistors N
41
and P
41
are connected with each other, and receive a select signal S. The drains of the transistors N
41
and P
41
are connected with each other, and connected to the gate of the transistor N
31
. The source of the transistor N
41
is grounded, whereas the source of the transistor P
41
is connected to the power source.
The inverters
5
and
600
supply the transfer gates
100
and
200
with complementary sampling control signals C and CB, in accordance with a sampling signal SA.
The inverter
5
includes a transistor (N-channel MOS transistor) N
51
and a transistor (P-channel MOS transistor) P
51
. The gates of the transistors N
51
and P
51
are connected with each other, and receive a sampling signal SA. The drains of the transistors N
51
and P
51
are connected with each other, and connected to the tr
Hayes & Soloway PC
NEC Corporation
Nguyen John
Young Brian
LandOfFree
Analog switch and A/D converter having the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Analog switch and A/D converter having the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Analog switch and A/D converter having the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3057365