Analog state recovery technique for DLL design

Details Analog state recovery technique for DLL design Analog state recovery technique for DLL design

2005-01-11

2005-01-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S149000

Reexamination Certificate

active

06842057

ABSTRACT:
A method and apparatus stores a voltage potential generated by a delay locked loop in order to reduce the time required for the delay locked loop to recover from a lost clock state. A clock path is arranged to carry a clock signal. The delay locked loop operatively connects to the clock path where the delay locked loop is arranged to generate a voltage potential dependent on a phase difference between the clock signal and a delayed clock signal output of the delay locked loop. An analog state storage apparatus operatively connects to the delay locked loop and is arranged to store the voltage potential. Also, the analog state storage apparatus is arranged to output the stored voltage potential to the delay locked loop in response to a loss of at least one of the clock signal and the delayed clock signal.

REFERENCES:
patent: 6018259 (2000-01-01), Lee
patent: 6166990 (2000-12-01), Ooishi et al.
patent: 6510191 (2003-01-01), Bockelman
patent: 6680874 (2004-01-01), Harrison

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