Analog signal processing circuit with integrated gain and timing

Details Analog signal processing circuit with integrated gain and timing Analog signal processing circuit with integrated gain and timing

1997-07-11

1999-12-21

Psitos, Aristotelis M.

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

360 46, G11B 509

Patent

active

060057297

ABSTRACT:
A Class IV Partial Response Maximum Likelihood data channel for analog signal processing of a disk drive signal in tracking mode includes a signal error generating circuit for "folding" the analog disk drive signal around the three PR-IV target values of +1, -1 and 0. Using the smaller error signal rather than the larger analog disk drive signal by which the disk drive signal deviates from the target values results in significant power saving with no reduction in electronic signal to noise ratio. An integrated error generating circuit generates both a gain error signal and a timing error signal from the folded error signal for feedback control of the data channel variable gain amplifier and variable clock oscillator. Shared processing of the timing and gain error signals results in power savings and simpler circuitry.

REFERENCES:
patent: 3728699 (1973-04-01), Sordello
patent: 5459757 (1995-10-01), Minuhin et al.
patent: 5796358 (1998-08-01), Shih et al.
patent: 5841602 (1998-11-01), Kanegae et al.

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