Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Patent
1998-03-06
2000-04-18
Vo, Don N.
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
H04L 700
Patent
active
060524227
ABSTRACT:
An analog signal offset cancellation circuit comprising a front end device, a comparator, a sampling device, a resampling clock generator and a recovery data generator is disclosed. In this offset cancellation circuit, the front end device receives an input analog signal. The comparator then compares the input analog signal with a threshold voltage to obtain an output binary signal. The sampling device samples the output binary signal by a sampling signal having a frequency N times that of the output binary signal to obtain sample data. The resampling clock generator then continually reads 2N samples of the sample data and outputs a two period resampling clock with its rising and falling edges determined by the edges and the number of uninterrupted logic one samples of the 2N samples. The resampling clock remains unchanged when the 2N samples are all logic one or all logic zero. The recovery data generator then samples the output binary signal using the resampling clock to obtain recovery data.
REFERENCES:
patent: 5068628 (1991-11-01), Ghoshal
patent: 5455847 (1995-10-01), Guilford et al.
patent: 5831456 (1998-11-01), Sutardja
Phu Phuong
Vo Don N.
Winbond Electronics Corp.
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