Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-04-30
2003-08-19
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S124000
Reexamination Certificate
active
06608583
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog input circuit to be used as an input stage of an analog signal processing apparatus such as a display device for displaying a video image by receiving a video signal.
2. Description of the Related Art
A conventional video input circuit for a video signal processing apparatus, as an analog signal input circuit, generally has the constitution shown in a block diagram in FIG.
1
. In other words, such an analog/digital converting circuit comprises a clamping circuit
11
, amplifying circuit
12
, low pass filter
13
, and sample-hold and analog/digital converter
14
.
An input video signal (VIN) and signals for the clamp setting voltage (VRCL) and clamp pulse (CLP) are input to the clamping circuit
11
. Moreover, the input video signal (VIN) is supplied via a capacitor (not shown) to the clamping circuit
11
.
The clamping circuit
11
is a circuit for clamping the input video signal to a certain voltage for a prescribed period. In other words, the clamping circuit
11
outputs the input video signal (VIN) as a video signal clamped to the clamp setting voltage (VRCL) just for the period designated by the clamp pulse (CLP).
The video signal clamped by the clamping circuit
11
is applied to the non-inverting input terminal of the amplifying circuit
12
. The amplifying circuit
12
comprises an operational amplifier and a plurality of resistors and switches. One end of each of the plurality of resistors is connected to the clamp setting voltage (VRCL) through the switches. Moreover, the clamp setting voltage (VRCL) is generated by the resistance division of two reference voltages, not shown, for determining the conversion range of the sample-hold and analog/digital converter
14
. The plurality of resistors and switches have the function of adjusting the amplification rate of the amplifying circuit
12
. The output of the amplifying circuit
12
is supplied to the sample-hold and analog/digital converter
14
through the low pass filter
13
.
The sample-hold and analog/digital converter
14
is a circuit for sample holding the analog signal supplied from the low pass filter
13
in response to a prescribed sampling clock train, and then generating digital data expressing the amplitude of the sample-held analog signal.
It is to be understood the amplitude of a video signal varies depending on its circumstance such as TV tuner, VTR and disc player. However, the analog/digital conversion range of the sample-hold and analog/digital converter
14
is self-determined. In the analog/digital converting circuit of
FIG. 1
, the level of amplification A becomes no more than one because the level of amplification A of the amplifying circuit
12
is determined with the following relationship according to resistance values R
1
and RN constituting the resistor group.
A=
1+(
R
1
/
RN
)
Consequently, it is a problem a video signal having an amplitude of, for example, 1.5 V or greater cannot be processed with a conventional input circuit when the analog/digital conversion range of the sample-hold and analog/digital converter
14
is up to 1.5 V. Especially for new image recording media such as DVD (digital versatile disc), the amplitude of the video signal tends to be diversified and it is necessary to contrive countermeasures for that.
For the so-called pipeline analog/digital converter, which is noteworthy as the latest analog/digital converter for video signal processing, it is often the case that the analog/digital converting range is 1.0 V. Meanwhile, the amplitude of conventional, standard video signals is about 1.3 V and therefore a problem is that those conventional, standard video signals cannot be connected to the pipeline analog/digital converter without an appropriate level adjustment.
Furthermore, in a conventional analog/digital converting circuit, the clamp setting voltage (VRCL) is used as the reference voltage for the amplifying circuit
12
and that voltage and the amplified output of the video signal are connected through the resistor group of the amplifying circuit
12
. As a result, it is a problem that changes in the amplified output of the video signal influences the clamp setting voltage (VRCL) and the clamp level in the clamping circuit
11
changes.
SUMMARY OF THE INVENTION
The present invention was made in order to solve such problems, and it is an object of the present invention to provide an analog signal input circuit for analog signal processing with which the amplification rate of the analog signal can be set to one or less and a stabilized clamping voltage is attained.
The analog input circuit according to the present invention comprises: a clamping circuit for clamping the amplitude of the input analog signal according to a clamping voltage setting signal; a sample-hold circuit for amplifying, and sampling and holding the output signal from the above-mentioned clamping circuit at the prescribed amplification rate; and an analog/digital converter for generating digital data expressing the amplitude of the output signal from the above-mentioned sample-hold circuit;
wherein the above-mentioned sample-hold circuit comprises a switch capacitor type of amplifier provided with a plurality of capacitors connected with a switch group, for which the opening and closing is controlled according to an amplification rate setting command, provided as input side capacitors or feedback side capacitors; and the above-mentioned prescribed amplification rate is established according to the capacitance ratio of the above-mentioned input side capacitors and feedback side capacitors based on the above-mentioned setting command; and
wherein the above-mentioned clamping circuit generates the above-mentioned clamping voltage setting signal, so that the central value of the amplitude of the output signal of the above-mentioned sample-hold circuit becomes the central voltage of the conversion range of the above-mentioned analog/digital converter according to the above-mentioned setting command.
REFERENCES:
patent: 4982191 (1991-01-01), Ohta
patent: 2001-45325 (2001-02-01), None
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
Young Brian
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