Analog signal amplifier circuit using a differential pair of...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

Reexamination Certificate

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C327S052000, C327S053000

Reexamination Certificate

active

06194921

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an analog signal amplifier circuit integrated on a semiconductor integrated circuit and, more specifically, to an analog signal amplifier circuit using a differential pair of MOSFETs (insulated-gate field effect transistors) in an input stage.
In most prior art semiconductor integrated circuits, a voltage-amplitude limiter circuit (limiter amplifier) and a voltage comparator circuit (comparator) for amplifying an analog signal, which are called an analog signal amplifier circuit, are each constituted of a bipolar transistor.
The trend is to constitute an analog signal amplifier circuit using MOS transistors in place of bipolar transistors with recent technological advances. However, the mutual conductance gm of a MOS transistor is smaller than that of a bipolar transistor and has a characteristic that it is proportionate to both the (½)th power of a drain current and the (½)th power of the ratio of gate width to gate length of the transistor. Therefore, an analog signal amplifier circuit using a differential pair of PMOS transistors M
1
and M
2
in an input stage, as shown in
FIG. 1
, has the following problem.
If the mutual conductance gm of the above PMOS transistors M
1
and M
2
is tenfold in order to achieve a high gain, the drain current or the gate width should be increased hundredfold in view of the above characteristic, which produces a bad effect of greatly increasing the current consumption and the area of an integrated circuit. Such an amplifier circuit is thus impractical.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to provide a signal amplifier circuit capable of easily achieving a high gain without greatly increasing the current consumption or the area of an integrated circuit even when a differential pair of MOS transistors is used in an input stage.
In order to attain the above object, there is provided a signal amplifier circuit comprising:
a first differential pair of a first MOS transistor of a first conductivity type and a second MOS transistor of the first conductivity type, a source of the first MOS transistor and a source of the second MOS transistor being connected to each other;
a first constant-current source connected to a common source-connection node of the first and second MOS transistors of the first differential pair;
a first bias supply source connected to a drain of the first MOS transistor and connected in series to a third transistor whose drain and gate are connected to each other and a fourth MOS transistor of a second conductivity type whose drain and gate are connected to each other;
a fifth MOS transistor of the second conductivity type constituting a first current mirror circuit together with the fourth MOS transistor, a gate and a source of the fifth MOS transistor being connected to the gate and source of the fourth MOS transistor, and a drain of the fifth MOS transistor being connected to a drain of the second MOS transistor;
a second bias supply source connected to the drain of the second MOS transistor and connected in series to a sixth transistor whose drain and gate are connected to each other and a seventh MOS transistor of the second conductivity type whose drain and gate are connected to each other;
an eighth MOS transistor of the second conductivity type constituting a second current mirror circuit together with the seventh MOS transistor, a gate and a source of the eighth MOS transistor being connected to the gate and source of the seventh MOS transistor, and a drain of the eighth MOS transistor being connected to the drain of the first MOS transistor;
a second differential pair of a ninth MOS transistor of the second conductivity type and a tenth MOS transistor of the second conductivity type, a source of the ninth MOS transistor and a source of the tenth MOS transistor being connected to each other, a gate of the ninth MOS transistor being connected to a drain of the first MOS transistor, and a gate of the tenth MOS transistor being connected to the drain of the second MOS transistor; and
a second constant-current source connected to a common source-connection node of the ninth and tenth MOS transistors of the second differential pair.
The signal amplifier circuit according to the present invention is virtually increased in conductance. If, therefore, the first and second current mirror circuits are varied in current mirror ratio, an arbitrary high gain can be obtained.
If, in particular, a plurality of MOS transistors are added as loads of the first and second MOS transistors constituting the first differential pair, a higher gain can be achieved.
If, furthermore, the ratio of gate width to gate length of each of the ninth and tenth MOS transistors constituting the second differential pair, is caused to differ from that of gate width to gate length of each of the MOS transistors constituting the first and second bias supply sources, an arbitrary high gain can be achieved.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 5552729 (1996-09-01), Deguchi
patent: 5602509 (1997-02-01), Kimura
patent: 5712594 (1998-01-01), Kimura
patent: 5764086 (1998-06-01), Nagamatsu et al.
patent: 5999055 (1999-12-01), Kimura
patent: 9-74340 (1997-03-01), None

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