Analog semiconductor memory device having multiple-valued compar

Details Analog semiconductor memory device having multiple-valued compar Analog semiconductor memory device having multiple-valued compar

1995-11-09

1997-11-04

Nelms, David C.

Static information storage and retrieval

Floating gate

Multiple values

365 45, 341136, 341159, G11C 1600, H03M 112

Patent

active

056847386

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a semiconductor device, and in particular to a high-performance CMOS circuit.


BACKGROUND ART

Source-follower circuits are frequently used to drive impedance loads, especially in applications employing analog or multiple-valued signals. Such a circuit is depicted in FIG. 1. This diagram indicates a source-follower circuit comprised of one NMOS transistor (abbreviated as "NMOS") (N1) and a load capacitance (C.sub.L); when N1 is turned on, the current I.sub.D increases V.sub.OUT until ##EQU1## where .gamma. is the body effect coefficient, V.sub.SB is the differential source-body voltage, and .phi.F is defined by: ##EQU2## E.sub.f is the Fermi level of the semiconductor, E.sub.i is the intrinsic Fermi level, and q is the charge of an electron.
A problem of this circuit arises if the output voltage is desired to be equal to the input voltage. In the case of a source-follower circuit, if the body of the NMOS is biased at 0 V, then V.sub.SB will increase as the output voltage rises. This will cause V.sub.T to rise, even if V.sub.TO =0 V. This phenomenon is called the "body effect". Therefore, V.sub.OUT is always less than V.sub.IN for a source follower containing an enhancement-mode NMOS.
Another drawback of the source-follower circuit is its slow transient characteristics. As V.sub.OUT rises, the transistor's gate-source differential voltage V.sub.GS (=V.sub.IN -V.sub.OUT) decreases, causing a reduction in the channel conductivity, which in turn reduces the drain current I.sub.D. Therefore, the amount of current available to pull up V.sub.OUT continuously decreases. This results in the transient characteristics shown in FIG. 2.
The present invention was created in order to solve the problems stated above; it has as an objective thereof to provide a semiconductor device which makes possible the full restoration of the source-follower output to equal its input voltage, and also decreases the time required for the output to reach its maximum value. In addition, this invention can also be used to convert the analog output of a source-follower circuit into a digital form.


DISCLOSURE OF THE INVENTION

The present invention discloses a semiconductor circuit comprising at least an MOS transistor. A multiple-valued data line, which is capable of M discrete voltage levels, or an analog data line rises (or falls) from an initial voltage to its final voltage. The inputs of M-1 comparators are connected to said data line, the outputs of said comparators are coupled capacitively to the input gate of a source-follower circuit, and the output of said source-follower circuit is fedback to the data line.
By means of the above semiconductor circuit, the time necessary for the data line to reach its final voltage is drastically reduced. Furthermore, the voltage of the data line can be easily converted to a binary-digital form with this circuit.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual diagram showing a typical NMOS source-follower circuit.
FIG. 2 is a graph showing time dependence of the output voltage of an NMOS source follower.
FIG. 3 is a conceptual diagram showing the circuit of Embodiment 1.
FIG. 4 is a graph showing the simulation data of the circuit of Embodiment 1. In FIG. 4 SAB is sence and boost.
FIG. 5 is a conceptual diagram showing the circuit of Embodiment 2.
FIG. 6 is a conceptual diagram showing the circuit of Embodiment 3.
FIG. 7 is a conceptual diagram showing the circuit of Embodiment 4.
FIG. 8 is a conceptual diagram showing the circuit of Embodiment 5.
FIG. 9 is a conceptual diagram showing the circuit of Embodiment 6.


BEST MODE FOR CARRYING OUT THE INVENTION

Herein below, the present invention will be explained in detail based on embodiments; however, the present invention is of course not limited to these embodiments.
This invention is used in a multiple-valued system containing M voltage levels. The lowest voltage level (Level 0) is determined to be equal to V.sub.SS, and the highest voltage level (Level M-1) is determined to be equ

REFERENCES:
patent: H1035 (1992-03-01), Haviland et al.
patent: 5192879 (1993-03-01), Aoki et al.
patent: 5376935 (1994-12-01), Seligson

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