Analog read and write paths in a solid state memory device

Details Analog read and write paths in a solid state memory device Analog read and write paths in a solid state memory device

2010-07-02

2011-11-29

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S189070, C365S189080, C365S196000, C365S210120

Reexamination Certificate

active

08068366

ABSTRACT:
A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O interface comprises a plurality of analog data paths that each includes a capacitor for storing charge corresponding to a target voltage to which a selected memory cell, coupled to its respective data path, is to be programmed. A plurality of comparators can be included in the I/O interface, with each such comparator coupled to a respective bit line. Such a comparator can compare a threshold voltage of a selected memory cell to its target voltage and inhibits further programming when the threshold voltage equals or exceeds the target voltage.

REFERENCES:
patent: 5907501 (1999-05-01), Hwang
patent: 5973956 (1999-10-01), Blyth et al.
patent: 6208542 (2001-03-01), Wang et al.
patent: 6865186 (2005-03-01), Jackson et al.
patent: 2007/0211529 (2007-09-01), Santis et al.

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