Analog PLL circuit and method of controlling the oscillation of

Oscillators – Ring oscillators

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Details

331 1A, 331 34, 331 74, 327263, 327264, 327158, 327159, H03B 500, H03L 709

Patent

active

061149179

ABSTRACT:
The present invention provides an analog PLL circuit able to shorten a lockin time during which oscillating frequency and phase of a voltage controlling oscillator settle.
An analog PLL circuit according to the present invention comprises a divider, a phase comparator, a charge pump, a low pass filter, a voltage controlling oscillator, and a divider. The voltage controlling oscillator has a ring oscillator composed of a plurality of logic inverting elements capable of changing the delay amount. During the reset period, the initial voltage is inputted to the voltage controlling oscillator via the analog switch, and the initial delay amount is set to each of the logic inverting elements. After the reset period finishes, at the point when the rising edge of the standard input signal is firstly inputted, the output of the D flip-flop becomes high level and the ring oscillator begins the oscillating operation.

REFERENCES:
patent: 5257294 (1993-10-01), Pinto et al.

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