Analog phase locked loop

Details Analog phase locked loop Analog phase locked loop

1987-08-19

1989-02-07

Pellinen, A. D.

Pulse or digital communications

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375111, 370100, 331 1A, H03D 324

Patent

active

048037052

ABSTRACT:
A phase locked loop for synchronizing a local digital signal with an incoming data signal is described. Parallel phase and frequency detectors compare the local and incoming signals and generate control pulse signals for controlling the frequency of a voltage controlled oscillator which generates the local digital signal. Logic circuitry is included in both the phase and frequency detectors for adjusting the generated control pulse signals in the event of detection of elongated pulse widths of the incoming data signal, indicating one of either an absence of incoming data signal or a bipolar violation in the event the data signals are ASI encoded. The phase locked loop is characterized by quick pull-in time, large pull-in frequency range, accurate clocking and low cost.

REFERENCES:
patent: 3878334 (1975-04-01), Halpern
patent: 4110557 (1978-08-01), Huber
patent: 4242639 (1980-12-01), Boone
patent: 4574243 (1986-03-01), Levine

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