Analog multiplier using triple-tail cell

Details Analog multiplier using triple-tail cell Analog multiplier using triple-tail cell

1997-11-24

1999-07-20

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical analog calculating computer

Particular function performed

327357, G06G 716

Patent

active

059250941

ABSTRACT:
An analog multiplier that decreases the circuit current consumption is provided. This multiplier includes a first triple-tail cell of first, second, and third transistors driven by a first tail current, and a second triple-tail cell of fourth, fifth, and sixth transistors driven by a second tail current. First and second constant current sources supplies first and second constant currents to the third and sixth transistors, respectively. The first and second tail currents are controlled by first and second tail current controllers, respectively The first and second tail current controllers controls the first and second tail currents so that the current changes of the third and sixth transistors are canceled, respectively, where the current changes are caused by the second input voltage applied across the input terminals of the third and sixth transistors.

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Y.H. Kim et al., "Four-Quadrant CMOS Analogue Multiplier", Electronics Letters, vol. 28, No. 7, Mar. 26, 1992, pp. 649-650.

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