Analog multiplier and multiplier core circuit used therefor

Details Analog multiplier and multiplier core circuit used therefor Analog multiplier and multiplier core circuit used therefor

1995-06-12

1998-01-27

Mai, Tan V.

Boots, shoes, and leggings

327359, G06G 716

Patent

active

057128103

ABSTRACT:
A multiplier core circuit having a novel circuit configuration, which is preferable for LSI. The circuit contains a quadritail circuit formed of first, second, third and fourth transistors whose emitters or sources are coupled together. Collectors or drains of the first and fourth transistors are coupled together and collectors or drains of the second and third transistors are coupled together. A sum of first and second input signals to be multiplied is applied to a base or gate of the first transistor with regard to a reference point. The first input signal is applied to a base or gate of the second transistor with regard to said reference point. The second input signal is applied to a base or gate of the third transistor with regard to the reference point. Neither the first input signal nor the second input signal are applied to a base or gate of the fourth transistor. An output signal showing multiplication result of the first and second input signals is differentially derived between the collectors or drains of the first and fourth transistors and the collectors or drains of the second and third transistors.

REFERENCES:
patent: 5107150 (1992-04-01), Kimura
patent: 5187682 (1993-02-01), Kimura
patent: 5444648 (1995-08-01), Kimura
K. Bult et al., "A CMOS Four-Quadrant Analog Multiplier", IEEE Journal of Solid-State Circuits, Jun. 1986, vol. SC-21, No. 3, pp. 430-435.
Z. Wang, "Novel Linearisation Technique for Implementing Large-Signal MOS Tunable Transconductor", Electronic Letters, Jan. 18, 1990, vol. 26, No. 2, pp. 138-139.
P. Wu et al., "Tunable Operational Transconductance Amplifier with Extremely High Linearity Over Very Large Input Range", Electronic Letters, Jul. 4.

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