Analog multiplex level shifter with reset

Details Analog multiplex level shifter with reset Analog multiplex level shifter with reset

2002-04-01

2004-04-27

Young, Brian (Department: 2871)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S145000

Reexamination Certificate

active

06727835

ABSTRACT:

TECHNICAL FIELD
This disclosure relates generally to transistor circuits and, more particularly, to digital-to-analog converters used for decoding and signal level shifting applications.
BACKGROUND
The liquid crystal display has become well known, driven in part by popular applications such as notebook computers, car navigational displays, and flat panel displays for personal computers. In each of these applications, a column driver circuit enables the operation of each liquid crystal display unit. Liquid crystal displays comprise a plurality of individual picture elements, called pixels, which are uniquely addressable in a row and column arrangement. The column driver circuitry provides the driving voltage to the columns of the liquid crystal display.
Column driver circuitry components act as intermediaries between the digital format of the electronics that process information and the analog format of the display that presents the results to the user. Accordingly, the column driver circuitry includes a digital-to-analog converter (“DAC”) that converts digital signals from the processing unit, bus, and memory into analog signals. However, DACs may be used in many applications other than in column driver circuitry.
One type of conventional DAC includes an inverter and a p-channel field effect transistor (“FET”) that is used as a feedback element for coupling a decoder circuit, which forms the input of the DAC, to an output stage such as, e.g., a multiplex switch, which forms the output of the DAC. One problem that occurs is that the FETs in a FET stack of the decoder circuit may have difficulty in driving the voltage level at the input of the inverter. As a result, the p-channel FET that forms the feedback element is formed with a large channel length, since the total resistance of the FETs in the FET stack has to be less than the resistance of the feedback FET. This large channel length requires substantial die space.
SUMMARY
In one embodiment of the invention, a digital to analog converter comprises a current source, a level shifter coupled to the current source, a stack of transistors coupled to the level shifter, wherein the stack of transistors is responsive to a reset signal, and an output stage coupled to the level shifter, wherein the output stage includes a transistor forming a path between a reference voltage level and an output voltage.
In another embodiment of the invention, a digital to analog converter comprises a decoder means, and an output means coupled to the decoder means.
In yet another embodiment of the invention, a digital to analog converter comprises a decoder stage, including a level shifter stage coupled to a decoder stage output, and a current source coupled to the level shifter, and an output stage coupled to the decoder stage.
In still another embodiment of the invention, a digital to analog converter comprises a decoder stage including a current source, a level shifter, and a stack of transistors, wherein the level shifter comprises an inverter with a feedback channel, and an output stage coupled to the decoder stage, the output stage including a transistor forming a path between a reference voltage level and an output voltage.


REFERENCES:
patent: 5296755 (1994-03-01), Miyamoto et al.
patent: 5465054 (1995-11-01), Erhart
patent: 5510748 (1996-04-01), Erhart et al.
patent: 5528256 (1996-06-01), Erhart et al.
patent: 5572211 (1996-11-01), Erhart et al.
patent: 5574475 (1996-11-01), Callahan, Jr. et al.
patent: 5578957 (1996-11-01), Erhart et al.
patent: 5604449 (1997-02-01), Erhart et al.
patent: 5703617 (1997-12-01), Callahan, Jr. et al.
patent: 5719591 (1998-02-01), Callahan, Jr. et al.
patent: 5726676 (1998-03-01), Callahan, Jr. et al.
patent: 5754156 (1998-05-01), Erhart et al.
patent: 5818252 (1998-10-01), Fullman et al.
patent: 5852426 (1998-12-01), Erhart et al.
patent: 6040815 (2000-03-01), Erhart et al.
patent: 6049246 (2000-04-01), Kozisek et al.
patent: 6118261 (2000-09-01), Erdelyi et al.

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