Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2007-04-17
2007-04-17
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S389000
Reexamination Certificate
active
10905436
ABSTRACT:
Circuits and methods are provided for reducing the voltage stress applied to the drain to source conduction path of an FET and/or to reduce the stress to the gate oxide of an FET which may have a thin gate oxide. Thus, in a current mirror circuit disclosed herein, a first field effect transistor (FET) has a first gate and a first drain, in which the first drain is conductively connected to a current source for conducting a first current. The current mirror circuit also includes at least one second FET having a second gate conductively connected to the first gate, in which the second FET is operable to output a second current in fixed proportion to the first current. A switching element having a first conductive terminal is connected to the first gate and to the second gate, the second conductive terminal being connected to the first drain of the first FET. A switching network is operable to controllably switch the first and second FETs and the third switching element between a powered on state in which the first and second currents are conducted and the third switching element is conducting, and a powered off state in which the first and second currents are not conducted and the third switching element is nonconducting such that the same drain to source voltage stress is applied to both first and second FETs.
REFERENCES:
patent: 5369312 (1994-11-01), Oh et al.
patent: 5726589 (1998-03-01), Cahill et al.
patent: 6377075 (2002-04-01), Wong
patent: 6630818 (2003-10-01), Comer et al.
patent: 6825710 (2004-11-01), Moyal
Gangasani Gautam
Hsu Louis L.
Selander Karl D.
Zier Steven J.
Capella Steven
International Business Machines - Corporation
Neff Daryl
Nuton My-Trang
LandOfFree
Analog MOS circuits having reduced voltage stress does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Analog MOS circuits having reduced voltage stress, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Analog MOS circuits having reduced voltage stress will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3734841