Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2000-09-06
2001-09-11
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185090, C365S045000
Reexamination Certificate
active
06288934
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an analog memory device, such as EPROM, EEPROM and flash memory. More particularly, the present invention relates to method and circuit for reading analog data stored in a memory cell array.
BACKGROUND OF THE INVENTION
Three common types of non-volatile memory, such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and flash memory use charge on a memory cell's floating gate to control the threshold voltage of the memory cell and indicate the state of the cell. Typically, binary memory cells have two states, one indicated by a high threshold voltage and one indicated by a low threshold voltage. Gathering electrons on a memory cell's floating gate increases the cell's threshold voltage and is referred to as writing or programming the memory cell. Erasing a memory cell removes electrons from the floating gate and reduces the threshold voltage.
A conventional flash memory includes a memory array, a slow ramp circuit, a column decoder, a row decoder, a sense amplifier, a pulse generating circuit and a sample and hold circuit. The flash memory array includes a large number of memory cells, each storing analog data as its threshold gate voltage, such as an audio signal continuously changing in level with the passage of time. The slow ramp circuit is connected at output terminals to the column decoder and sample and hold circuit. The slow ramp circuit supplies a control gate voltage, which is increased continuously or step-wise from a predetermined lowest level. The control gate voltage may be decreased continuously or step-wise from a predetermined highest level.
The column decoder is connected at an output terminal to the flash memory array to select a column including a selected memory cell. The row decoder is connected at an input terminal to the flash memory array and at an output terminal to the sense amplifier. When the control gate voltage applied to the selected memory cell increases and reach its threshold level, a drain current starts flowing through the selected memory cell. Such a drain current is supplied to the sense amplifier.
The sense amplifier is connected at an output terminal to an input terminal of the pulse generating circuit. The sense amplifier detects the drain current of the selected memory cell and reverses its output when the current exceeds a predetermined threshold level. The pulse generating circuit is connected at an output terminal to another input terminal of the sample and hold circuit. In response to the output signal of the sense amplifier, the pulse generating circuit generates and supplies a sampling signal to the sample and hold circuit. The sample and hold circuit samples and holds the control gate voltage supplied from the slow ramp circuit in response to the sampling signal from the pulse generating circuit. The sample and hold circuit supplies such a control gate voltage, corresponding to the threshold gate voltage of the selected memory cell, as an analog output signal.
According to the conventional analog memory, however, some error signals may be outputted when the flash memory array includes some failure bits. If such a conventional analog memory is used in a voice recorder, noise sounds would be made.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide method and circuit for reading analog data stored in memory cells, in which failure signals are prevented from being outputted.
Another object of the present invention is to provide an analog memory device, in which failure signals are prevented from being outputted.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a read-out circuit, includes a data detecting circuit which detects analog data of a selected memory cell; a data condition deciding circuit which decides whether or not the analog data detected by the data detecting circuit is in a normal range; and a controller which normalizes an output signal for the selected memory cell in accordance with the decision of the data condition deciding circuit.
According to a second aspect of the present invention, a method includes detecting data of a selected memory cell; deciding whether or not the detected data of the selected memory cell is in a normal range, and normalizing an output signal for the selected memory cell in accordance with the decision.
According to a third aspect of the present invention, an analog memory device is provided with a read-out circuit according to the above described first aspect of the present invention.
REFERENCES:
patent: 5606522 (1997-02-01), Chai
patent: 5638320 (1997-06-01), Wong et al.
patent: 6151246 (2000-11-01), So et al.
patent: 8-125719 (1996-05-01), None
patent: 2000-68833 (2000-03-01), None
Hoang Huan
Jones Volentine PLLC
OKI Electric Industry Co., Ltd.
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