Television – Image signal processing circuitry specific to television – Chrominance-luminance signal separation
Reexamination Certificate
2000-03-10
2003-05-06
Kostak, Victor R. (Department: 2611)
Television
Image signal processing circuitry specific to television
Chrominance-luminance signal separation
C348S714000, C348S615000, C365S045000
Reexamination Certificate
active
06559895
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an analog memory, and more particularly, it relates to a technique to reduce fixed pattern noise occurring in an output signal of the analog memory. Also, it relates to an image processing system using the analog memory.
BACKGROUND ART
The CMOS-LSI technique has been greatly developing as is generally known, and an analog memory is one of the devices used in the field of analog CMOS-LSI design. An analog memory is a circuit, similar to a digital memory, for storing an input analog signal in a storage element in a specified address and outputting an analog signal stored in a storage element in a specified address.
FIG. 7
is a diagram for showing the basic configuration of a conventional analog memory. As is shown in
FIG. 7
, the analog memory includes an address generation unit
10
, a storage unit
20
including plural storage elements
21
, an input circuit
30
and an output circuit
40
. One storage element
21
of the storage unit
20
is specified in accordance with an address selection signal SL output from the address generation unit
10
. In reading a signal, an analog signal stored in the specified storage element
21
is output as a voltage signal Vout. In writing a signal, an input voltage signal Vin is stored in the specified storage element
21
.
PROBLEMS TO BE SOLVED
In the analog memory, a capacity element is generally used as a storage element. However, since a capacity element is easily affected by noise, an offset voltage Vnoise resulting from accumulation of noise in the capacity element is added to the input voltage Vin of the analog memory. It is known that the offset voltage Vnoise is varied depending upon the physical position of a storage element. Specifically, assuming that the storage element has an address n, the output voltage Vout can be represented by the following formula (1):
Vout=Vin+Vnoise (
n
) (1)
In other words, the offset voltage Vnoise is represented as a function of the address n of the storage element. Such an offset voltage Vnoise(n) is generally designated as fixed pattern noise.
The fixed pattern noise becomes a serious obstacle when the analog memory is used in image signal processing. In a system dealing with an image signal, the specification of the SN ratio is as strict as −60 dB or less because the eyes of a human being are very sensitive to brightness. Noise appears on a screen unless the fixed pattern noise of the analog memory is reduced so as to satisfy the specification. However, the specification of −60 dB or less is very difficult to attain in an analog circuit.
Various developments have been made so far (for example, Document 1: Matsui, K., T. Matsuura, et al., “CMOS video Filters Using Switched Capacitor 14 MHz Circuits”, IEEE J. Solid-State Circuits, pp. 1096-1101, 1985; and Document 2: Ken A. Nishimura, Paul R. Gray, “A Monolithic Analog Video Comb Filter in 1.2-um CMOS”, IEEE Journal of Solid-State Circuits, VOL. 28, NO. 12, pp. 1331-1339, December 1993). However, such developments have not been put to practical use due to the fixed pattern noise described above. The problem of the fixed pattern noise has remained unsolved for more than 10 years since the first report.
DISCLOSURE OF THE INVENTION
The present invention was devised in view of the aforementioned problem, and an object is reducing the fixed pattern noise occurring within an analog memory so as to suppress the harmful influence on picture quality in using the analog memory in the image processing, whereby the analog memory is usable in an image processing system.
Specifically, the analog memory of this invention including plural storage elements for storing an analog signal, comprises an address generation unit for outputting an address selection signal for directing any of the plural storage elements to conduct a write or read operation, and transfer paths of the address selection signal between the address generation unit and the plural storage elements are constructed with a substantially uniform electric characteristic in driving the storage elements by the address selection signal to such an extent that an output signal of the analog memory is free from fixed pattern noise.
In the present analog memory, the electric characteristic in driving the respective storage elements by the address selection signal can be made uniform to the extent that the output signal of the analog memory is free from the fixed pattern noise. Accordingly, the charge feed through noise can be made substantially uniform between the storage elements, resulting in suppressing the fixed pattern noise occurring in the output signal of the analog memory.
Preferably, the analog memory further comprises temporary storage means for temporarily storing and outputting the address selection signal disposed between the address generation means and the storage elements, and the temporary storage means is constructed to have an output characteristic substantially uniform with respect to the storage elements.
Furthermore, it is preferred that the temporary storage means is provided with respect to each of the storage means and includes plural flip-flops having substantially the same characteristic. In this manner, the temporary storage means having an output characteristic substantially uniform with respect to the respective storage elements can be realized by a very simple circuit configuration.
Moreover, lines between the temporary storage means and the storage elements are preferably constructed to have substantially the same characteristic.
Further preferably, in the analog memory, plural storage elements are arranged in a two-dimensional array forming a storage unit, the address generation unit outputs, as the address selection signal, a row address selection signal for specifying a row of the storage elements in the array and a column address selection signal for specifying a column of the storage elements in the array, first temporary storage means for temporarily storing and outputting the row address selection signal is disposed between the address generation unit and each row of the storage unit, second temporary storage means for temporarily storing and outputting the column address selection signal is disposed between the address generation unit and each column of the storage unit, and the first temporary storage means is constructed to have an output characteristic substantially uniform with respect to the respective rows of the storage unit and the second temporary storage means is constructed to have an output characteristic substantially uniform with respect to the respective columns of the storage unit.
In this manner, the first and second temporary storage means for suppressing the fixed pattern noise occurring in the output signal of the analog memory are provided with respect to each row and each column of the storage unit. Therefore, as compared with the case where the temporary storage means is provided with respect to each storage element, the circuit scale and the power consumption can be reduced.
Moreover, it is preferred that lines between the first temporary storage means and the storage elements are constructed to have substantially the same electric characteristic, and that lines between the second temporary storage means and the storage elements are constructed to have substantially the same electric characteristic.
In addition, each of the storage elements preferably includes a capacity element; a logic circuit for receiving the row address selection signal and the column address selection signal; and an analog switch disposed between the capacity element and a signal line for transferring an input/output signal to be switched in accordance with an output signal of the logic circuit, and a line between the logic circuit and the analog switch is preferably constructed to have an electric characteristic substantially uniform between the storage elements.
Alternatively, the analog memory of this invention including plural storage elements for storing an analog signal, comprises
Dosho Shiro
Kurimoto Hidehiko
Okamoto Tatsuo
Ozasa Masayuki
Yanagisawa Naoshi
Kostak Victor R.
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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