Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2007-09-26
2010-10-05
Nguyen, Dang T (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S185250, C365S045000
Reexamination Certificate
active
07808857
ABSTRACT:
According to a preferred embodiment of the present invention, an analog memory includes a first to third memory blocks. Each of the first to third memory blocks includes a plurality of capacitive elements for storing electric charges corresponding to an input signal, an output line for transferring the electric charges, and a plurality of MOS transistors each for changing connection between the capacitive element and the output line. When a signal is outputted from the output line to a buffer circuit by sequentially connecting the capacitive element to the output line in the first memory block, all connections between the capacitive elements and the output line are disconnected in the second and third memory blocks with the output line of the first memory block and the output line of the second memory block connected.
REFERENCES:
patent: 4807168 (1989-02-01), Moopenn et al.
patent: 6061279 (2000-05-01), Toda et al.
patent: 6529049 (2003-03-01), Erhart et al.
patent: 2006-186562 (2006-07-01), None
Onaya Masato
Serizawa Shunsuke
Nguyen Dang T
Sanyo Electric Co,. Ltd.
Sanyo Semiconductor Co. Ltd.
Westerman Hattori Daniels & Adrian LLP
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