Analog macro embedded in a digital gate array

Details Analog macro embedded in a digital gate array Analog macro embedded in a digital gate array

1988-03-25

1989-05-23

LaRoche, Eugene R.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, H03L 708

Patent

active

048334251

ABSTRACT:
A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

REFERENCES:
patent: 4069462 (1978-01-01), Dunn
patent: 4227158 (1980-10-01), Schroeder et al.
patent: 4388597 (1983-06-01), Bickley et al.
patent: 4394769 (1983-07-01), Lull
patent: 4594563 (1986-06-01), Williams
patent: 4689581 (1987-08-01), Talbot

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