Analog hold cell in a CMOS process

Details Analog hold cell in a CMOS process Analog hold cell in a CMOS process

2002-07-02

2004-09-14

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S309000, C341S122000

Reexamination Certificate

active

06791374

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital circuit timing accuracy and, more particularly, to techniques for using hold cells in low power oscillators to maintain long-term timing accuracy in sleep mode without reliance on an external crystal.
2. Description of the Related Art
It is common for today's electronic devices to incorporate combinations of analog and digital circuitry. Many of these devices, such as cellular phones, operate in mobile environments where design characteristics are being pushed to meet higher consumer demands. These demands include smaller, more compact devices with longer battery life at a lower overall cost. In order to meet these demands, analog and digital circuitry should be combined more efficiently and in a manner that will reduce power consumption.
In an attempt to conserve power, many devices implement a sleep mode when not in use. It is known, for example, that incorporation of a sleep mode in cellular phone devices may extend battery life by up to a factor of 10. A key objective when designing portable electronic devices is to minimize the amount of current used while in sleep mode. In addition to minimizing the amount of current used while in sleep mode, the device should also be able to retain some level of timing accuracy for a minimum duration as dictated by the application.
To maintain the required level of timing accuracy while in sleep mode, most devices use a sleep mode oscillator. It is common in modem designs to use a low-power, low-frequency crystal on the printed circuit board for the sleep mode oscillator. This low-power crystal is external to the semiconductor chips and is present in addition to an external master crystal which is used during normal operation.
FIG. 1
, while not to scale, shows a prior art printed circuit board (PCB) device
101
, including a semiconductor chip
103
, an external master crystal
115
, and an external low-power crystal
117
. The semiconductor chip
103
may contain a digital core
105
, an analog component
107
, a digital component
109
, a radio frequency (RF) component
111
, or other circuitry
113
. The semiconductor chip
103
receives a signal
119
from either the master crystal
115
or the low-power crystal
117
, depending on the mode of operation.
The use of the second external low-power crystal
117
presents several disadvantages relative to design optimization. An obvious disadvantage is that the second external low-power crystal
117
takes up valuable space on the PCB device
101
.
FIG. 1
is not to scale; in actuality the external master crystal
115
and external low-power crystal
117
are of relatively large size, comparable to the size of the semiconductor chip
103
itself. Therefore, addition of the second external low-power crystal
117
can be significant to overall PCB device
101
size. Another disadvantage is that adding the second external low-power crystal
117
increases the expense of the overall PCB device
101
. A less obvious disadvantage is that the external low-power crystal
117
requires the semiconductor chip
103
to have a pin available for interface connection. As the semiconductor chip
103
has a limited number of pins available, dedication of a pin to the external low-power crystal
117
may be costly relative to design restrictions and complications. Furthermore, the routing required to connect the semiconductor chip
103
to the external low-power crystal
117
uses valuable PCB device
101
area and adds expense. Two objectives in the industry are to move toward smaller devices and minimize cost. Adding the second external low-power crystal
117
to the PCB device
101
does not comply with these two objectives. Therefore, the focus of attention is to remove the external low-power crystal
117
used to support the sleep mode of operation.
FIG. 2
shows the PCB device
101
from
FIG. 1
with the external low-power crystal
117
removed. Additionally,
FIG. 2
shows a low power oscillator (LPO)
121
receiving a clock reference signal
123
from the external master crystal
115
and providing a low frequency output signal
125
to the digital core
105
. As a substitute for the external low-power crystal
117
, one requirement of the LPO
121
is to derive a lower frequency signal from a higher frequency signal. The temperature stability of the LPO
121
is a typical consideration when replacing the external low-power crystal
117
. A feature of an on-board crystal is that changes in frequency due to changes in temperature are minimized, whereas a free-running oscillator will change in frequency significantly with temperature. However, one known method for designing the LPO
121
to be temperature stable is to use a conventional phase lock loop (PLL)
122
, as shown in FIG.
3
.
FIG. 3
shows the conventional PLL
122
used to derive a lower frequency signal from a higher frequency signal. The conventional PLL
122
takes an accurate clock reference signal
123
from the external master crystal
115
. The clock reference signal
123
is passed to a reference divider
129
, via a connection
127
, which divides the clock reference signal
123
down to a lower frequency signal. The output signal from the reference divider
129
is then passed to a phase frequency detector (PFD)
133
via a connection
131
. The PFD
133
generates an output signal which is passed through a connection
135
to control a charge pump
137
. The charge pump
137
, in turn provides an output signal which is passed through a connection
139
to control a voltage controlled oscillator (VCO)
145
. The VCO
145
provides a low frequency output signal
125
from the conventional PLL
122
via a connection
146
. The VCO
145
low frequency output signal
125
is also passed to an N-counter
149
, via a connection
147
. The N-counter
149
generates an output signal which is provided to the PFD
133
via a connection
151
. An N value of the N-counter
149
can be set arbitrarily; however, the N value remains fixed. Due to the conventional PLL
122
functionality, the VCO
145
output frequency is equal to the N value of the N-counter
149
times the N-counter
149
output frequency. The conventional PLL
122
function is to make both input signals to the PFD
133
match in both frequency and phase. The PFD
133
makes a decision on whether or not the VCO
145
output signal frequency should be higher or lower, depending on what is required to match the reference input signal frequency, received through connection
131
, to the N-counter
149
output signal frequency received through connection
151
. Thus, the conventional PLL
122
is a closed-loop, negative feedback circuit.
Due to the way the PFD
133
functions and the accuracy of the clock reference signal
123
entering the PFD
133
via the reference divider
129
, the accuracy of the VCO
145
low frequency output signal
125
will equal the accuracy of the clock reference signal
123
. Therefore, obtaining a desired low frequency output signal
125
accuracy is accomplished by requiring the clock reference signal
123
to have a better accuracy. In reality, external master crystal
115
accuracies are typically ±20 ppm which is sufficient for LPO
121
applications requiring output signal accuracies up to ±20 ppm.
Through use of the conventional PLL
122
featuring closed-loop, negative feedback, the consistent low frequency output signal
125
is derived from the clock reference signal
123
and is maintained regardless of changes in temperature. Thus, the closed-loop, negative feedback conventional PLL
122
alleviates the need for the additional external low-power crystal
117
to produce a low frequency reference clock signal to be used in sleep mode. However, power conservation while in sleep mode requires that the external master crystal
115
be turned off.
One feature of the conventional PLL
122
is that it has a flywheel effect. This means that once the loop is locked, if the loop is broken, the output of the VCO
145
will stay at

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