Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-10-09
2007-10-09
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C341S118000
Reexamination Certificate
active
11279251
ABSTRACT:
An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.
REFERENCES:
patent: 6014258 (2000-01-01), Naka et al.
patent: 6414611 (2002-07-01), Nagaraj
patent: 6545626 (2003-04-01), Nakada
patent: 2003/0034984 (2003-02-01), Murata
patent: 475333 (2002-02-01), None
Chou Yu-Pin
Gong Jin-Sheng
Tsai Jui-Yuan
Wang Chi-Feng
Hjerpe Richard
Hsu Winston
Lesperance Jean
Realtek Semiconductor Corp.
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