Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2002-10-10
2003-11-04
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000, C341S156000, C341S161000, C341S162000
Reexamination Certificate
active
06642871
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates an analog/digital converter having an error automatic calibration function.
2. Description of the Related Art
A pipeline-connection analog/digital (A/D) converter is used for carrying out analog/digital conversion at a high speed. In a pipeline-connection A/D converter, digital outputs of pipeline-connected analog stages are summed up by pipeline-connected adders in order to increase the speed of the conversion. At the same time, there is a demand for enhancement of the precision of digital data obtained as a result of the analog/digital conversion. In order to improve the precision, there has been proposed a method of correcting errors caused by the analog/digital conversion technique and hardware implementing the analog/digital converter. In accordance with an A/D conversion technique whereby an analog signal is divided into three segments separated from each other by a threshold and codes of
1
and
0
are assigned to the two segments, if the threshold includes an error component, an analog signal close to the threshold is converted into digital data having poor precision. In order to solve this problem, there has been proposed an A/D conversion technique such as a 1.5-bit A/D conversion technique as is described in the IEEE Journal of Solid-State Circuit, Vol. 34, No. 5, May 1999 and the IEEE Communication Magazine, October 1999 whereby an analog level is divided into three or more segments and a digital value is assigned to each of the segments. The IEEE journal and the IEEE magazine are referred to hereafter as reference 1 and reference 2 respectively.
In accordance with the 1.5-bit A/D conversion technique, the level of an analog signal in the range [−VR, VR] is divided into three segments, namely, segment
0
, segment
1
and segment
2
, which cover levels in the ranges [−VR, −VR/
4
], [−VR/4, VR/4] and [VR/4, VR] respectively. A/D conversion is carried out by summing up digital values assigned to segments
0
,
1
and
2
.
Each stage comprises a sub-ADC (sub-analog/digital converter), a sub-DAC (sub-digital/analog converter), an adder and an operational amplifier. The sub-ADC outputs a segment number indicating which of segments
0
to
2
the level of an analog signal is in. The sub-DAC outputs a second analog signal corresponding to the segment number to the adder. For example, in the case of segment
0
, a VR/2 second analog signal is output to the adder. In the case of segment
1
, a
0
second analog signal is output to the adder and, in the case of segment
2
, a −VR/2 second analog signal is output to the adder. The adder adds the second analog signal to the analog signal. The operational amplifier amplifies the output of the adder at a predetermined gain of typically
2
and outputs the amplified signal to the next stage.
In the case of a stage with such a configuration, an error is inevitably generated in digital data obtained as a result of conversion of an input analog signal due to a gain error of an amplifier and mismatching caused by variations in capacity of a capacitor employed in the adder. It is thus necessary to correct the error. Reference 2 discloses correction of errors by correction of the error of the gain of the amplifier at an analog circuit level. Japanese Patent Laid-open No. Hei 11-274927 discloses a technique of correction whereby mismatching of a capacitor at each stage and an error of the gain of an amplifier at each stage are measured and converted into digital data to be stored in a memory. The digital data obtained as a result of the measurement is multiplied by digital data obtained as a result of conversion to find an error term, which is added to the digital data obtained as a result of conversion. Japanese Patent Laid-open No. Hei 11-274927 is referred to as reference 3.
Since the error correction technique disclosed in reference 2 is a technique to correct an error at an analog level, however, there is raised a problem of a complicated analog circuit. In the case of the correction disclosed in reference 3, a correction value for correcting a difference in capacitor storage capacity and for correcting an error of the gain of an amplifier needs to be computed by multiplication each time A/D conversion is carried out. Since the multiplication of a correction value consumes much power in comparison with addition and subtraction processing and a bit-shift operation, however, there is raised a problem that a battery is exhausted in a short period of time caused by the large power consumption for devices requiring low power consumption. An example of such devices is a mobile phone.
SUMMARY OF THE INVENTION
It is thus an object of the present invention to provide an A/D converter having an error automatic calibration function capable of reducing power consumption.
In accordance with an aspect of the present invention, there is provided an analog/digital converter comprising an analog conversion unit including a plurality of stages having a pipelined configuration and a digital conversion unit, wherein each of the stages includes: a sub-analog/digital converter for outputting a segment number corresponding to the level of a first analog signal; a sub-digital/analog converter for outputting a second analog signal corresponding to the segment number; and an amplifier circuit for adding the second analog signal to the first analog signal to produce a sum analog signal and amplifying the sum analog signal at a predetermined gain, and wherein the digital conversion unit includes: digital-value storage registers, which are each provided for one of the stages, each of the registers used for storing a digital value completing error correction for a segment and being adapted to output the digital value that corresponds to the segment number, an addition-processing unit for summing up the digital values output for all the stages from the specific digital-value storage registers to output digital-converted data; and an error-computation control unit for controlling the stages so that a specific one of the stages inputs an error computation analog signal, computing an error of the specific stage on the basis of the digital-converted data computed by the addition-processing unit by summing up the digital values output by the digital-value storage registers, in accordance with the segment numbers received from all the stages following the specific stage and updating the digital values stored in the digital-value storage registers associated with all the stages following the specific stage in order to cancel the error of the specific stage.
Preferably, the error-computation control unit controls the specific stage in order to compute an actual gain of the amplifier circuit employed in the specific stage from the digital-converted data, computes a ratio of the computed actual gain to an ideal gain of the amplifier circuit employed in the specific stage, and updates the digital values stored in the digital-value storage registers associated with all the stages following the specific stage.
Preferably, the error-computation control unit updates the digital value stored in the digital-value storage register which is associated with the specific stage and which is associated with a particular segment, so that the digital-converted data becomes equal to a predetermined digital value when an input analog signal at a particular level corresponding to the particular segment is supplied to the specific stage.
The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent and the invention itself will be best understood from a study of the following description and appended claims with reference to attached drawings showing some preferred embodiments of the invention.
REFERENCES:
patent: 4535319 (1985-08-01), Penney
patent: 4908621 (1990-03-01), Polonio et al.
patent: 5043732 (1991-08-01), Robertson et al.
patent: 5047772 (1991-09-01)
Kobayashi Yuji
Takeyabu Masato
Fujitsu Limited
Katten Muchin ZavisRosenman
Khai Nguyen
Tokar Michael
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