Analog-digital converter utilizing multiple ramp integrating tec

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324 99D, 340347M, 340347AD, 364829, H03K 1302

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active

043618316

ABSTRACT:
An analog current I.sub.1, to be digitized is fed continuously to the input of an integrator. Two pulse counters, serially connected, algebraically count pulses from a pulse generator, the first pulse counter of the two setting, upon overflow, a bistable element to one of its states. The bistable element will remain in the state until the first pulse of the pulse generator, after the next change-over of the threshold switch occurs. In accordance with the state of the threshold switch, the bistable flip-flop circuit permits either a current I.sub.2, or a current I.sub.3 (the two currents being of opposite polarity) to be applied, simultaneously with the current I.sub.1, to the integrator by suitable switches during predetermined time intervals W. The time interval W is defined as the sum of the timing intervals occurring between two successive overflow pulses of the second counter during which I.sub.2 is simultaneously integrated with current I.sub.1, less than the sum of the timing intervals during which current I.sub.1 is integrated with current I.sub.3. A digital value corresponding to the analog value of current I.sub.1 is then stored, in the form of pulse counts. Unlike the somewhat similar coverter of U.S. Pat. No. 3,765,012, the digital value obtained does not become constant, but settles down to a fluctuation of .+-.1/2 unit, thus providing less resolution to an extent proportional to the period of the pulse generator. Successive values of the fluctuating result can be combined automatically in a following calculating circuit to provide a refined value having an additional decimal place, with an increase of resolution that depends upon the number of successive values combined.

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patent: 3879724 (1975-04-01), McDonald
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