Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2003-02-26
2004-06-15
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000, C341S118000, C341S120000
Reexamination Certificate
active
06750800
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog-digital converter and a method for converting a data of the same and, particularly, to an analog-digital converter which eliminates an adverse effect caused by a residual electric charge of a sampling capacitor which the analog-digital converter comprises, and a method for converting a data of the same.
2. Description of the Prior Art
In recent years, information processors based on a digital technique have come into heavy usage in society at large. On the other hand, equipment such as sensors and the like has been utilizing analogue voltage values. To utilize such analogue values in the information processors based on the digital technique, analogue-digital converters are required. The conversion of such analogue values into digital values is frequently performed by the analog-digital converters (hereinafter, abbreviated as [A/D converter]). Moreover, various controllers for performing the processing subsequent to the analogue-digital conversion are also well known.
In general, the controllers such as those described above comprise a plurality of analogue input terminals, a channel selector portion which is provided in the input portion of the A/D converter and selects one analogue input terminal from among a plurality of analogue input terminals, and a sampling capacitor which holds a voltage of the selected analogue input terminal until an A/D converting operation is completed.
In the case where such an A/D converter is built into some device and an open-failure occurs due to some reason while the device is actually used, since the A/D converter is not provided with an discharge circuit, the voltage of the channel which is A/D converted is put into a state of being held in the sampling capacitor at a point of the time before the failure occurs.
In this case, since the residual voltage of the sampling capacitor is A/D converted and the A/D converted voltage is outputted as an erroneously converted value, this will sometimes cause a malfunction of the device having the built-in A/D converter.
As a counter measure to cope with such a problem, though it is contemplated to add a discharge switching circuit to the outside of the device, this will create a new problem of the complication of the device structure and the cost-up thereof.
Further, as another counter measure, a method is contemplated in which a constant voltage is applied to each of the analogue input terminals through a high resistance, and a discharge is made at the constant voltage when the open failure occurs.
However, since this method uses the high resistance, the time constant of the discharge circuit becomes high, and a considerable amount of time is required from the occurrence of the open failure to the completion of the discharge. For this reason, during this time, if an erroneous conversion value is loaded, it ends up with the same state where no counter measure has been taken, thereby causing a malfunction of the device.
On the other hand, if the discharge circuit is not set to the high resistance, a margin of error due to potential voltages with sensors or signal sources becomes high, thereby creating a problem in the degree of accuracy.
For this reason, as means for solving such problems, there have been proposed various means. For example, the analogue digital-converter, which solves such problems, is described in Japanese Utility Model Laid-Open No. 7-33033.
Shown in
FIG. 1
is a structure of this analogue-digital converter. Referring to
FIG. 1
, this analogue-digital converter comprises an analog-digital conversion portion
901
; a channel selection portion
902
comprising a plurality of channels CH1 (
909
), CH2 (
910
) to CHn and switches
906
,
907
,
908
connected to each channel CH1 to CHn; a switch
905
connected in series to each switch
906
,
907
,
908
and connected in series to the analogue-converting portion
901
; and a sampling capacitor
904
extended between the switch
905
and the ground.
In this analog-digital converter, one channel CHn of the channel selection portion
902
is connected to the ground as a discharge channel, and prior to the A/D conversion in other channels, the discharge channel CHn is selected to discharge the residual voltage of the sampling capacitor
904
.
Further, a sample and hold circuit as shown in
FIG. 2
has been described in Japanese Patent Laid-Open No. 4-7914.
This sample and hold circuit comprises a plurality of channels CH1 (
1009
), CH2 (
1010
) to CHn (
1011
); a channel selection portion
1002
comprising switches
1006
,
1007
,
1008
which are connected in series to each channel CH1 to CHn;
a switch
1005
connected in series to each switch
1006
,
1007
,
1008
and also to an output terminal
1001
; a sampling capacitor
1004
extended between the switch
1005
and the ground; a charging and discharging circuit
1013
connected to a node between the switch
1005
and the output terminal
1001
; and a switch
1012
provided between the node and the charging and discharging circuit
1013
.
In this sample and hold circuit, the sampling capacitor
1004
is added with the charging and discharging circuit
1013
and, prior to the sampling period of time, the sampling capacitor
1004
is initialized to a predetermined voltage by the charging and discharging circuit
1013
so as to eliminate the influences from the channels which were previously A/D converted.
Further, shown in
FIG. 3
is the analog-digital converter described in Japanese Patent Laid-Open No. 2000-338159.
The analogue-digital converter shown in
FIG. 3
comprises plural pairs of channel terminals
1102
; first circuits
1101
connected to each of the plural pairs of channel terminals
1102
; a amplifier
1103
connected in series to each of the first circuits
1101
; an analog-digital converter
1110
connected to an output terminal of the amplifier
1103
; a sampling capacitor Cs extended in parallel to two input terminals of the amplifier
1103
; and a discharging switch SWd connected in parallel to the sampling capacitor Cs between two input terminals of the amplifier
1103
.
Each of the first circuits
1101
comprises resistors Ri
1
, Ri
2
connected respectively to plural pairs of channel terminals
1102
; switches SWi connected in series respectively to resistors Ri
1
, Ri
2
; and capacitors Ci connected in parallel to resistors Ri
1
, Ri
2
.
In this analog-digital converter, the sampling capacitor Cs is added with the discharging switch SWd, and the discharging switch SWd is turned ON prior to the sampling period of time, so that a residual voltage of the sampling capacitor Cs is discharged.
However, these prior arts have been carrying problems as described below.
A first problem is that one channel is wasted from the analog input channels.
The reason why is because, as shown in
FIG. 1
, one channel CHn is connected to the ground as a discharging channel. Accompanied with the complexity and deepening upgrading of the system including the A/D converters, the number of sensors and other signal sources are also increasing. At the same time, there are demands that the number of terminals of the A/D converters or LSIs with built-in A/D converters is limited to the minimum possible in view of the cost or the mounting area involved. Besides, there are often the cases where even one channel cannot be wasted.
A second problem is that the prior arts are at a disadvantage in the cost or the consumption current involved. The reason why is because, as shown in
FIG. 2
or
3
, in order to discharge the residual voltage of the sampling capacitors
1004
, Cs, there arise a demand for newly adding the charging and discharging circuit
1013
or the charging switch SWd to the analog-digital converter.
A third problem is that the prior arts can discharge the voltage of the sampling capacitor only to some fixed electric potential.
The reason why is because the prior arts connect one channel CHn to the ground (
FIG. 1
) or are constituted such that the discharge is made by the cha
Katten Muchin Zavis & Rosenman
Mai Lam T.
NEC Electronics Corporation
Tokar Michael
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