Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-03-22
2002-06-25
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000
Reexamination Certificate
active
06411247
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an analog/digital converter (hereinafter, referred to as “ADC”) for converting an analog voltage into a digital signal and, more particularly, to a technique for preventing errors which are caused due to external noises of a dual-slope conversion type ADC.
2. Related Background Art
FIG. 2
is a constructional diagram of a conventional dual-slope conversion type ADC.
The dual-slope conversion type ADC has an analog switch
1
for switching an input voltage Vi as a conversion target and a reference voltage−Vr and inputting the switched voltage. An operational amplifier
2
constructing a voltage follower is connected to an output side of the analog switch
1
. An output side of the operational amplifier
2
is connected to an inversion input terminal of an operational amplifier
4
through a resistor
3
. A capacitor
5
and an analog switch
6
are connected in parallel between the inversion input terminal of the operational amplifier
4
and its output terminal. A non-inversion input terminal of the operational amplifier
4
is connected to a base voltage GND. The output side of the operational amplifier
4
is connected to a first input terminal of a voltage comparator
7
. A second input terminal of the voltage comparator
7
is connected to the base voltage GND and its output side is connected to a control circuit
8
.
The control circuit
8
generates control signals C
1
and C
6
to the analog switches
1
and
6
and generates a control signal C
9
to a counter
9
on the basis of an output signal S
7
of the, voltage comparator
7
. The counter
9
counts the number of clock signals (not shown) in response to the control signal C
9
. A count value of the counter
9
is outputted as a digital signal OUT corresponding to the input voltage Vi.
FIG. 3
is a signal waveform diagram showing the operation of the circuit shown in FIG.
2
. In
FIG. 3
, a solid line indicates an integration voltage V
4
on the output side of the operational amplifier
4
in the case where the input voltage Vi is large, and a broken line shows the integration voltage V
4
in the case where the input voltage Vi is small.
First, for a reset period from time
0
to time T
0
, the analog switch
6
is short-circuited by the control signal C
6
which is generated from the control circuit
8
and the capacitor
5
is discharged. Since the non-inversion input terminal of the operational amplifier
4
is connected to the base voltage GND, an electric potential at the inversion input terminal is also set to the base voltage GND and the integration voltage V
4
is set to the base voltage GND (that is, 0V).
Subsequently, at time T
0
, the analog switch
6
is opened by the control signal C
6
. and the input voltage Vi side of the analog switch
1
is selected :by the control signal C
1
. Thus, a current which is supplied from the output side of the operational amplifier
2
to the resistor
3
is set to Vi/R (where, R is a resistance value of the resistor
3
).
In the ideal operational amplifier
4
, since the electric potential at the inversion input terminal is equal to the base voltage GND and an input impedance is infinite, the whole current flowing in the resistor
3
is charged into the capacitor
5
. Thus, the integration voltage V
4
after the elapse of a predetermined time t
1
of the first integration period is equal to −(1/CR)Vi·t
1
(where, C is a capacitance of the capacitor
5
).
A second integration period is started at time T
1
after the elapse of time t
1
from time T
0
. The control signal C
9
to start the counting operation is generated from the control circuit
8
to the counter
9
and the analog switch
1
is switched to the reference voltage −Vr side by the control signal C
1
. Therefore, a current of −Vr/R is supplied from the output side of the operational amplifier
2
to the resistor
3
.
The integration voltage V
4
after the elapse of time t
2
from time T
1
is expressed by the following equation (1).
V
4
=−(1
/CR
)
Vi·t
1
+(1
/CR
)
Vr·t
2
(1)
When the integration voltage V
4
is equal to the base voltage GND, the signal S
7
is generated from the voltage comparator
7
to the control circuit
8
. The control circuit
8
stops the control signal C
9
, thereby stopping the counting operation of the counter
9
. From the equation (1), time t
2
is expressed by the following equation (2).
t
2
=(
Vi/Vr
)t
1
(2)
Since Vr and t
1
are set to predetermined values, time t
2
is proportional to the input voltage Vi and the digital signal OUT which is outputted from the counter
9
is equal to a value that is proportional to the input voltage Vi.
However, the conventional dual-slope conversion type ADC has the following problem.
When noises are inputted from the outside during the converting operation, the voltage that is charged into the capacitor
5
is influenced. Since the first integration period has been preset to the predetermined time, if the period is set to a value that is integer times as long as a presumed period of power noises or the like, a positive component and a negative component of the noises can be set off. Since the second integration period, however, changes in proportion to the input voltage Vi, the external noises cannot be set off. There is, consequently, a problem that a conversion error is caused by the external noises.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to solve the problem of the conventional technique and provide a dual-slope conversion type ADC which is hardly influenced by external noises.
According to the first aspect of the invention, the above object is accomplished by an analog/digital converter (ADC) comprising: switching means for switching an analog voltage as a conversion target and a reference voltage whose polarity is different from that of the analog voltage and sequentially outputting them; integrating means for continuously integrating the analog voltage and the reference voltage which are outputted from the switching means and forming an integration voltage; first comparing means for comparing the integration voltage with a base voltage and outputting a first comparison result; second comparing means for comparing the integration voltage with a voltage that is higher than the base voltage by a predetermined voltage and outputting a second comparison result; third comparing means for comparing the integration voltage with a voltage that is lower than the base voltage by a predetermined voltage and outputting a third comparison result; counting means for counting a time which is required from a start of the integration of the reference voltage in the integrating means to a timing when the first comparison result is inverted and outputting a count result as a digital signal corresponding to the analog voltage; first measuring means for measuring a difference between the inversion time of the first comparison result and that of the second comparison result; second measuring means for measuring a difference between the inversion time of the first comparison result and that of the third comparison result; and comparing means for comparing measurement results of the first and second measuring means and discriminating whether a difference between them lies within the permission value or not.
According to the first aspect of the invention, since the ADC is constructed as mentioned above, the following operation is executed.
First, the analog voltage as a conversion target is outputted from the switching means and integrated by the integrating means. Subsequently, the reference voltage is outputted from the switching means and continuously integrated by the integrating means. The integration voltage formed by the integrating means is compared with the base voltage by the first comparing means and the first comparison result is outputted. The time which is required from the start of the integration of the reference voltage by the integrating means to the inversion o
Jeanpierre Peguy
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
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