Analog delay circuit configuration

Details Analog delay circuit configuration Analog delay circuit configuration

1992-09-30

1995-01-17

Wolfe, Willis R.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327399, H03H 1126

Patent

active

053828402

ABSTRACT:
An analog delay circuit configuration includes a switching stage. A capacitor is connected upstream of the switching stage. A controlled current source has a current being definitive for a charging state of the capacitor. The current source is clocked with a pulse-to-interval ratio of less than 1. A current mirror configuration reduces the current of the current source. An inverter stage is coupled to the current mirror configuration and has an output side connected to the capacitor.

REFERENCES:
patent: 4812687 (1989-03-01), Larson et al.
patent: 4837466 (1989-06-01), Kanauchi
patent: 5006738 (1991-04-01), Usuki et al.
patent: 5028824 (1991-07-01), Young
patent: 5057722 (1991-10-01), Kobatake
patent: 5300837 (1994-04-01), Fischer

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