Analog delay chain having more uniformly distributed...

Amplifiers – With semiconductor amplifying device – Including differential amplifier

Reexamination Certificate

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C330S311000

Reexamination Certificate

active

10928420

ABSTRACT:
A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.

REFERENCES:
patent: 5418497 (1995-05-01), Martin
patent: 6023192 (2000-02-01), Didier
patent: 6504432 (2003-01-01), Rokhsaz
patent: 2004/0189387 (2004-09-01), Okamoto
patent: 2006/0028275 (2006-02-01), Bhattacharjee et al.
patent: 2006/0061415 (2006-03-01), Bhattacharjee et al.
patent: 2006/0091954 (2006-05-01), Darabi

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