Analog current memory

Details Analog current memory Analog current memory

1994-01-25

1995-03-21

Fears, Terrell W.

Static information storage and retrieval

Analog storage systems

365233, G11C 1300

Patent

active

054002737

ABSTRACT:
An analogue current memory arrangement includes an input (30) and an output (33). A first (coarse) current memory cell (T31,S31,C31) senses the input current during clock phase .phi.1a and reproduces the sensed current during clock phases .phi.1b and .phi.2. A second (fine) current memory cell (T32,C32,S32) acts as a current source during phase .phi.1a when a reference voltage (VR) is applied to the gate of transistor (T32). The second current memory cell senses the difference between the input current and the output of the first current memry cell during phase .phi.1b and reproduces the sensed current during phase .phi.2.
During phase .phi.2 the input switch (S30) is opened and the output switch (S34) is closed causing the combined outputs of the first and second current memory cells to be fed to the output (33).
(FIGS. 3 and 4).

REFERENCES:
patent: 3315236 (1967-04-01), Hewlett
"A Switched Current Technique for High Performance", Electronics Letters, vol. 29, No. 16, 5 Aug. 1993, Stevenage GB pp. 1400-1401, (Hughes et al.).

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