Coded data generation or conversion – Analog to digital conversion followed by digital to analog...
Reexamination Certificate
1999-09-29
2002-04-23
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to digital conversion followed by digital to analog...
C341S116000, C341S158000, C341S143000, C341S162000, C341S059000, C341S141000
Reexamination Certificate
active
06377194
ABSTRACT:
The present application describes a hybrid distributed analog computational scheme, which carries out computations in distributed analog computational blocks and performs digital signal restoration of the analog signal at specified intervals between the analog computational stages.
BACKGROUND
Computation is often carried out by encoding information in physical state variables. The information contained in those variables is then processed using physical computation devices.
Analog variables are continuously variable between a lower limit and an upper limit. Digital variables, on the other hand, have only two values and those values matter only at certain times. In synchronous systems, those times coincide with some part of a clock pulse.
Digital systems have been extensively used for computation. Digital systems often show superior noise immunity as compared with analog systems. However, a digital signal is processed using Boolean algebra. This allows logical relationships such as AND, OR, NOT, NAND and XOR in which the transistor is simply used as a switch. Hence, a single transistor carries out a relatively small amount of computation when this scheme is used.
Analog systems can use the inherent properties of the underlying physical technology in which they are implemented. For example, primitives like Kirchoff's voltage and current laws can be used to add two analog signals. Multiplication can be done using the multiplicative relationship between charge (Q), current (I) and time (t), i.e. Q=I·t. Such schemes allow much more computation to be done with a single element, e.g., a single transistor.
On the other hand, noise and offset can become a problem in analog systems. The noise in analog systems is typically additive. A cascade of analog stages will inevitably accumulate noise if a sufficiently large amount of analog processing is performed.
As an example of the above, addition of two real numbers with 8-bit resolution can be done with one wire in an analog circuit, using Kirchoff's current. 16 bit addition would be almost (2
8
)
2
times harder to implement in terms of power or area for the same analog circuit—the resources required by analog computations scale exponentially with the precision of the computation. The same 8-bit addition operation would typically take 224 transistors in a CMOS parallel digital adder circuit. However, 16-bit digital addition would only consume twice as much power, area or time an 8-bit digital addition—the resources needed for digital computations scale as a linear or polynomial function of the precision of the computation.
SUMMARY
The present application combines the advantageous parts of these two technologies by defining a hybrid scheme which uses the advantageous parts of both systems. The hybrid method uses a distributed analog system to compute, along with a discrete digital signal-restoration system to restore and preserve the information in analog signals. Like digital systems, this system uses different circuit portions to calculate different portions of the solution to a problem. Hence, the hybrid system uses the same kind of “divide-and-conquer” approach that is currently used by digital technology to achieve solutions that scale as a linear or polynomial function of the precision required by the computation. However, the computation is done with analog real-valued primitives, not with logical digital primitives, thus more efficiently exploiting the computational primitives inherent in the technology.
The present system uses a plurality of analog processors, each of which has less resolution than is necessary for the precision of the final answer. For example, an 8-bit precise computation requiring 2
8
=256 resolvable levels would be calculated by two analog processors which have 4 bits of analog resolution each, or 4 processors with 2 bits of analog resolution each. The analog processors each compute only a portion of the total solution. They are associated with one another and interact with one another. Since the analog processors operate at relatively low precision, their power consumption and area consumption is low.
The analog processors are combined with elements that achieve noise reduction via signal restoration.
The signal restoration is performed by an analog-to-digital-to-analog converter that restores the analog signal to one of M discrete attractor levels. The input signal is compared with various threshold levels and restored to an attractor state that is closest to the input value.
REFERENCES:
patent: 3656152 (1972-04-01), Gundersen
patent: 4763107 (1988-08-01), Koen et al.
patent: 5041831 (1991-08-01), Bohley et al.
patent: 5543795 (1996-08-01), Fernald
patent: 6262678 (2001-07-01), Sarpeshkar
California Institute of Technology
Fish & Richardson P.C.
Mai Lam T
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