Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2008-07-29
2008-07-29
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
07405720
ABSTRACT:
An analog buffer circuit which has small input and output offsets and reduced power consumption even if it is formed on an insulating substrate by TFTs, a display device which uses the analog buffer circuit as a peripheral driving circuit for a display unit, and a portable terminal in which the display device is provided as a screen display unit are provided. By performing offset detection on a source follower in such a manner that, for example, two capacitors Cn1and Cn2are connected to the gate of a NMOS transistor Qn11as a source follower, and conduction
onconduction control of switches Sn1to Sn5are performed, if needed, and by sequentially canceling the detected offsets, a final offset voltage is sufficiently reduced and high precision offset cancellation is realized.
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Kida Yoshitoshi
Maekawa Toshikazu
Nakajima Yoshiharu
Depke Robert J.
Hjerpe Richard
Rockey Depke & Lyons, LLC
Said Mansour M
Sony Corporation
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