Analog buffer circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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Details

C327S379000, C327S389000, C326S082000

Reexamination Certificate

active

07622964

ABSTRACT:
An analog buffer circuit (10) includes a first p channel field effect transistor (11), an n channel field effect transistor (12) and a second p channel field effect transistor (13). The transistors are connected to one another in serial between power supplying terminals (VDD and GND). The transistors have gates connected to an input terminal (IN) in common. An output terminal (OUT) is connected to a connecting point between the n channel transistor and the second p channel transistor. With this structure, output voltage which appears on the output terminal is approximately proportional to input voltage supplied to the input terminal.

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patent: 6198334 (2001-03-01), Tomobe et al.
patent: 6437611 (2002-08-01), Hsiao et al.
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patent: 2005/0168250 (2005-08-01), Lin
patent: 2006/0214713 (2006-09-01), Matsuoka
patent: 7-191303 (1995-07-01), None
Rail-to-rail low-power high-slew-rate CMOS analogue buffer Carrillo, J.M.; Carvajal, R.G.; Torralba, A.; Duque-Carillo, J.F.; Electronic Letters, vol. 40, Issue 14, Jul. 8, 2004 pp. 843-844.

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