Analog BiCMOS multiplexers with CMOS control signals

Details Analog BiCMOS multiplexers with CMOS control signals Analog BiCMOS multiplexers with CMOS control signals

2000-09-11

2002-04-09

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S099000, C327S407000, C257S276000

Reexamination Certificate

active

06369637

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to fast analog BiCMOS multiplexers (MUX) with CMOS control signals and particularly to the elimination of cross-signal feed-through in these high speed circuits.
2. Brief Description of the Known Art
FIG. 1
shows a fully differentially BiCMOS MUX which can be used to accommodate a wide varying common mode input signal for accomplishing fast analog multiplexing. In this circuit, two differential input signals INP
1
, INM
1
and INP
2
, INM
2
are converted to current by means of bipolar transistors
1
-
2
and resistors
5
-
6
or transistors
3
-
4
and resistors
7
-
8
depending on whether control signal SEL or SELB is selected and then this current is presented at resistors
9
or
10
, respectively. Current always flows in current sources
11
-
14
and is routed by means of NMOS signal control switches
15
-
18
or is dumped to the supply via NMOS switches
19
-
22
. The two output signals OUTP and OUTM are developed by coupling the signals from node N
1
(transistor
17
—resistor
9
connection) and node N
2
(transistor
18
—resistor
10
connection) to respective source followers comprised of bipolar transistors
23
and
24
and current sources
25
and
26
, respectively. This circuit has good common mode characteristics, but is limited in performance by internal parasitic capacitances. It should also be noted that this circuit could be implemented using only CMOS circuitry, although the circuit would be slower and have higher distortion.
Analog multiplexers, used to select one of several input signals, often have undesirable signal feed-through where an attenuated level of an unselected signal appears as part of the output signal. This is due primarily to the parasitic capacitances associated with the CMOS transistors used to implement the control switches. As a result, this undesirable feed-through causes a degradation at the output of both signal-to-noise and dynamic range for the selected signal. Also, due to the parasitic capacitances at the nodes of the control switches, these circuits are often limited to the number of input signals which can be multiplexed.
Thus, there is a need for an improved high-speed MUX which eliminates the cross-signal feed-through problems of the prior art. The invention and embodiments disclosed herein address this need.
For further reference, U.S. Pat. No. 5,744,995 discusses multi-input multiplexer and U.S. Pat. No. 5,598,114 discusses high-speed multiplexers.
SUMMARY OF THE INVENTION
This invention addresses the shortcomings of conventional analog multiplexers to provide low distortion, high speed solutions with a high input-to-output signal multiplexing ratio. Two embodiments address the signal feed-through issue using BiCMOS circuitry; one with emphasis on improving a more conventional multiplexer circuit and the other using a new diode controlled approach. The first embodiment of this invention addresses the problem of parasitic capacitance in the reference circuit discussed in the prior art and significantly improves this circuit's performance by means of the CMOS control transistor layout to provide a faster multiplexer, although one which limits the number of input signals which can be multiplexed. A second embodiment uses an entirely new approach to develop a high-speed BiCMOS multiplexer with a large multiplexing ratio and low signal feed-through. In general, these designs take into account such parameters as input signal level, signal bandwidth, common mode operation, parasitic capacitance, and transistor layout. Both of these techniques can be applied to both single-ended and/or differential configurations.


REFERENCES:
patent: 6081006 (2000-06-01), Nelson

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