Analog and multi-level memory with reduced program disturb

Details Analog and multi-level memory with reduced program disturb Analog and multi-level memory with reduced program disturb

1996-07-22

1998-10-06

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518523, G11C 1604

Patent

active

058187570

ABSTRACT:
Applying a bias voltage to unselected word-lines reduces program disturb of the threshold voltages of unselected memory cells during a write to a non-volatile memory. Applying the bias voltage only to memory cells which have already been written with threshold voltages higher than a minimum value and not to erased (or virgin) memory cells allows the bias voltage to be higher without creating currents through unselected memory cells. Data such as a series of samples representing a continuous analog signal can be recorded by writing to sequential addresses to fill one row in an array with data before writing to the next row. Bias flag circuits in a row decoder of the memory indicate which rows are filled with data and therefore which word-lines should have the bias voltage applied during a write.

REFERENCES:
patent: 5267209 (1993-11-01), Yoshida
patent: 5280446 (1994-01-01), Ma et al.
patent: 5555521 (1996-09-01), Hamada et al.
patent: 5604711 (1997-02-01), Cheung
patent: 5619450 (1997-04-01), Takeguchi

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