Analog and aperiodic frequency divide-by-two circuit

Details Analog and aperiodic frequency divide-by-two circuit Analog and aperiodic frequency divide-by-two circuit

1984-02-29

1987-06-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072191, 307271, 307304, 328 15, 328 25, 455333, H03B 1900, H03K 1716

Patent

active

046706747

ABSTRACT:
A frequency divide-by-two circuit capable of operating from substantially DC up to the maximum operating frequency of the component devices. First and second mixer stages receive the signal to be divided and its antiphase complement. The mixer output signals are amplified and summed. A portion of the sum signal is fed back to the other inputs of the mixers. The mixing amplifying and summing functions can all be performed by two FETs each having two gates. The divider can be integrated on a single chip since it does not make use of a filter. It can be used at frequencies of up to about 25 GHz.

REFERENCES:
patent: 3716730 (1973-02-01), Cerny, Jr.
patent: 3938061 (1976-02-01), Levasseur et al.
patent: 4308473 (1981-12-01), Carnes
patent: 4511813 (1985-04-01), Pam
patent: 4540958 (1985-09-01), Neyens et al.
International Journal of Electronics, vol. 43, No. 2, Aug. 1977, pp. 185-191, A. Ammar et al.
Ahamed et al., "Frequency Divider-Multiplier Scheme for High Efficiency Microwave Power", IEEE Trans. on Communications, vol. COM-24, No. 2, pp. 243-249, Feb. 1976.

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