Analog active matrix emissive display

Details Analog active matrix emissive display Analog active matrix emissive display

1998-11-25

2002-07-09

Hjerpe, Richard (Department: 2774)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S076000, C345S078000, C345S080000

Reexamination Certificate

active

06417825

ABSTRACT:

TECHNICAL FIELD
The present invention relates, in general, to active matrix emissive displays and, more particularly, to an emissive display which uses an analog driving technique to display grayscale.
BACKGROUND OF THE INVENTION
Thin film active matrix electroluminescent (EL) (AMEL) displays are well known in the art and are used as flat panel displays in a variety of applications. A typical display includes a plurality of picture elements (pixels) arranged in rows and columns. Each pixel contains an EL cell having an EL phosphor active layer between a pair of insulators and a pair of electrodes. Additionally, each pixel contains switching circuitry that controls illumination of the cell. The electroluminescent display is one example of an emissive display. Other examples include field emissive displays and plasma displays.
One example of a prior art AMEL display is disclosed in U.S. Pat. No. 5,587,329, issued Dec. 24, 1996 to Hseuh et al. The disclosed AMEL display is shown in
FIG. 1
which depicts a schematic diagram of an AMEL display
100
. The AMEL display contains an arrangement of rows and columns of AMEL display pixels.
FIG. 1
depicts one of these AMEL display pixels
102
. In accordance with that disclosure, the pixel
102
contains an electric field shield
104
between a switching circuit
106
and an EL cell
108
.
As for the specific structure of the AMEL display pixel
102
, the switching circuit
106
contains a pair of transistors
110
and
112
that are switchable using a select line
114
and a data line
116
. To form circuit
106
, transistor
110
, typically a low voltage metal oxide semiconductor (MOS) transistor, has its gate connected to the select line
114
, its source connected to the data line
116
, and its drain connected to the gate of the second transistor
112
and, through a first capacitor
118
, to the electric field shield
104
. The electric field shield is connected to ground. The first capacitor is actually manifested as the capacitance between the shield
104
and the gate electrode of transistor
112
. To complete the switching circuit, transistor
112
, typically a high voltage MOS transistor, has its source connected to the data line
116
and its drain connected to one electrode of the EL cell
108
. A high voltage bus
122
connects the second electrode of the EL cell to a high voltage (e.g., 250 volts) alternating current (AC) source
120
.
The transistors used to form the switching circuit
106
may be of any one of a number of designs. Typically, the first transistor is a low breakdown voltage (less than 10 volts) MOS transistor. The second transistor is typically a double diffused MOS (DMOS) device having a high breakdown voltage (greater than 150 volts). The transistors can be either n- or p-channel devices or a combination thereof, e.g., two NMOS transistors, two PMOS transistors or a combination of NMOS and PMOS transistors.
In operation, images are displayed on the AMEL display as a sequence of frames, in either an interlace or progressive scan mode. During an individual scan, the frame time is subdivided into a separate LOAD period and an ILLUMINATE period. During the LOAD period, an analog-to-digital converter
124
and a low impedance buffer
126
produce data for storage in the switching circuitry. The data is loaded from the data line
116
through transistor
110
and stored in capacitor
118
. Specifically, the data lines are sequentially activated one at a time for the entire display. During activation of a particular data line, a select line is activated (strobed). Any transistor
110
, located at the junction of activated data and select lines, is turned ON and, as such, the voltage on the data line charges the gate of transistor
112
. This charge is primarily stored in capacitor
118
.
As the charge accumulates on the gate of transistor
112
, the transistor begins conduction, i.e., is turned ON. At the completion of the LOAD period, the high voltage transistor in each pixel that is intended to be illuminated is turned ON. As such, during the ILLUMINATE period, the high voltage AC source that is connected to all the pixels in the display through bus
122
is activated and simultaneously applies the AC voltage to all the pixels. However, current flows from the AC source through the EL cell and the transistor
112
to the data line
116
in only those pixels having an activated transistor
112
. Consequently, during the ILLUMINATE period of each frame, the active pixels produce electroluminescent light from their associated EL cells.
The operation of the AMEL display is also disclosed in U.S. Pat. No. 5,302,966 issued Apr. 12, 1994 and is incorporated herein by reference. As disclosed therein, during operation, the frame time is divided into separate LOAD periods and ILLUMINATE periods. During LOAD periods, data are loaded, one line at a time, from the data line through transistor
110
in order to control the conduction of transistor
112
.
During a particular data line ON, a select line is strobed. On those select lines having a select line voltage, transistor
110
turns on allowing charge from data line
116
to accumulate on the gate of transistor
112
thereby turning transistor
112
on. At the completion of a LOAD period the second transistors of all activated pixels are on. During the ILLUMINATE period the high voltage AC source
120
connected to all pixels, is turned on. Current flows from the source through the EL cell and the transistor
112
to the data line at each activated pixel, producing an electroluminescent light output from the activated pixel's EL cell.
The buffer amplifier
126
holds the voltage on the data line
116
at its nominal value during the ILLUMINATE period. The data which is capacitively stored on the gate of transistor
112
operates through transistor
112
to control whether the pixel will be white, black, or gray. If, for example, the gate of transistor
112
stores a 5 V level (select @ −5V and data @ 0V), then transistor
112
will conduct through both the positive and negative transitions of the input voltage at the bus
122
, which effectively grounds Node A. This allows all of the displacement current to flow from the input electrode
122
through the EL cell
108
, which in turn lights up the pixel. If the gate of transistor
112
stores a −5V level (select @ −5V and data @ −5V), then transistor
112
will remain off through all positive transitions of the input voltage at the input bus
122
. Transistor
112
thus behaves like a diode, which charges the capacitance associated with the EL cell, and quickly suppresses the flow of alternating current through the EL phosphor thereby turning the pixel off.
Gray scale control of each pixel is achieved by varying the voltage on the data line during each of the individual (typically 128) ILLUMINATE periods of each field of a frame. The voltage variation may be a linear ramp of the voltage, a step function in voltage, with each step corresponding to a level of gray. If, for example, the gate of transistor
112
stores a −1.5V gray-scale level (select @ −5V and V
th
=1V) and the data line is ramped linearly from 5V to −5V during the field, then transistor
112
will conduct for approximately 32 of the 128 ILLUMINATE sub-cycles resulting in a time-averaged gray-scale brightness of 25 %.
Note that the AMEL display pixel always operates digitally even when displaying gray-scale information. All transistors are either fully-on or fully-off and dissipate no power in either state. When a pixel is off, it simply acts as if it is disconnected from the resonant power source and therefore does not dissipate or waste any power.
Another method for providing greyscale control of the AMEL display comprises executing, during a frame time, a number of LOAD/ILLUMINATE periods (subframes). During the LOAD period of the first of these subframes, data corresponding to the least significant bit (LSB) is loaded into the circuitry of each pixel. During the

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