An improved semiconductor memory cell circuit and structure

Details An improved semiconductor memory cell circuit and structure An improved semiconductor memory cell circuit and structure

1975-10-30

1977-06-28

Curtis, Marshall M.

Communications: electrical

Digital comparator systems

357 44, G11C 1144

Patent

active

040329020

ABSTRACT:
An improved memory cell comprising a word line, a pair of bit lines, a pair of load impedances, and a pair of switching transistors. The pair of switching transistors each include an emitter coupled to a respective one of the bit lines, a base coupled to a respective one of the load impedances, and a collector coupled to the base of the other switching transistor. The pair of load impedances may include a pair of transistors each having an emitter coupled to the word line, a base coupled to a respective one of the emitters of the pair of switching transistors, and a collector coupled to a respective one of the bases of the switching transistors.

REFERENCES:
patent: 3423737 (1969-01-01), Harper
patent: 3643235 (1972-02-01), Berger et al.

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