An enhanced processor buffered interface for multiprocessor syst

Details An enhanced processor buffered interface for multiprocessor syst An enhanced processor buffered interface for multiprocessor syst

1995-06-01

1996-10-08

Tung, Kee M.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395309, 345213, G06F 1500

Patent

active

055640087

ABSTRACT:
An Enhanced Processor Buffered Interface (22c) for use in a multiprocessor system (10). The Enhanced Processor Buffered Interface executes an Atomic Fetch and Add operation for maintaining multiprocessor consistency and for minimizing the required participation of an attached processor (22a) in reading and writing locked memory locations, supports interleaved memory banks (22d) that operate with burst mode memory accesses at rates of up to 400 MBytes/sec, includes switchable state machines (52, 54, 100) to selectively provide wait-states as required for supporting different memory access timings, and furthermore provides an improved serial interface to an external multi-element LED display (110).

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