Amplifying circuit

Amplifiers – With semiconductor amplifying device – Including plural stages cascaded

Reexamination Certificate

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Details

C330S277000, C330S310000, C330S299000

Reexamination Certificate

active

07391269

ABSTRACT:
The invention provides an amplifying circuit for reducing electric power consumption at a standby mode time. Therefore, in DMOS and NMOS transistors constituting a cascode amplifier, the gate of the DMOS transistor of an initial stage is biased to a grounding voltage through a resistor, and the source of the DMOS transistor is connected to the output side of an inverter through an inductor. When a control signal is set to a level “H”, the output of the inverter becomes a level “L”, and the DMOS transistor attains a turning-on state and a sufficient operating electric current is flowed to the cascode amplifier. Thus, an input signal is amplified and is outputted as an output signal. In contrast to this, when the control signal is set to the level “L”, the output of the inverter becomes the level “H”, and the DMOS transistor attains a turning-off state and the operating electric current of the cascode amplifier is stopped.

REFERENCES:
patent: 4586004 (1986-04-01), Valdez
patent: 5282039 (1994-01-01), Vilard
patent: 5389892 (1995-02-01), Embree
patent: 6175264 (2001-01-01), Jinbo
patent: 6496074 (2002-12-01), Sowlati
patent: 6535065 (2003-03-01), Aoki
patent: 6636119 (2003-10-01), Vathulya
patent: 6819179 (2004-11-01), Raja et al.
patent: 07-193441 (1995-07-01), None
patent: 11-265593 (1999-09-01), None

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