Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-08-10
2003-03-04
Tokar, Michael (Department: 2819)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S251000, C330S253000, C330S254000, C330S260000, C330S261000, C330S258000
Reexamination Certificate
active
06529075
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to amplifier circuits, and specifically to highly-linear amplifiers.
BACKGROUND OF THE INVENTION
The need for designing highly-linear amplifiers has become acute during the last decade because of the increasingly precise specifications associated with modern integrated circuits, e.g., wireless equipment and sensitive test equipment. In particular, the suppression of higher-order harmonic distortion in these circuits is desirable, and has been only partially addressed in the prior art through the use of differential circuitry, distortion compensation methods, and deep global feedback.
U.S. Pat. No. 4,267,516 to Traa, U.S. Pat. No. 5,729,176 to Main et al., U.S. Pat. No. 5,126,586 to Gilbert, U.S. Pat. No. 4,287,478 to Berger, U.S. Pat. No. 4,390,848 to Blauschild, and U.S. Pat. No. 4,390,848 to Robert, which are incorporated herein by reference, describe various circuit designs for suppressing odd-order harmonics. In an article by Jensen, et al., entitled, “A 3.2 GHz Second Order Delta-Sigma Modulator Implemented in InP HBT Technology,”
IEEE Journal of Solid State Circuits,
30(10), October, 1995, which is incorporated herein by reference, a technique for compensating for odd-order harmonics is described.
These circuits provided by the prior art, although improving linearity, leave several issues unresolved which prevent achieving the linearity required by state-of-the-art specifications. First, even if a circuit is theoretically designed to be symmetric, in practice there are always asymmetries, caused by variations in manufacturing processes, which result in the appearance of even-order harmonics in the output spectrum of a circuit. Second, in the existing designs of compensation circuits, the amplitude and phase balance at higher frequencies is violated, and the desired compensation is consequently not achieved.
Reference is now made to
FIGS. 1
,
2
A,
2
B, and
2
C.
FIG. 1
is a schematic diagram of a prior art bipolar linear amplifier
20
, as depicted in the above-cited article by Jensen. This amplifier includes three blocks: a differential pair block
30
, a current-voltage block
40
, and an odd-order harmonic correction block
50
, shown respectively in
FIGS. 2A
,
2
B, and
2
C.
Block
30
(
FIG. 2A
) forms the basis of prior art amplifier 20. It includes transistors Q
1
and Q
2
, and a resistor R
1
, configured to form a first differential pair. The function of block
30
is to convert an input voltage signal V
IN
applied to the bases of the transistors into a nonlinear current I flowing through Q
1
and Q
2
.
Block
40
(
FIG. 2B
) includes transistors Q
6
and Q
7
in a common base structure. The emitters of Q
6
and Q
7
are connected to the collectors of transistors Q
1
and Q
2
, respectively. The function of block
40
is to convert the nonlinear collector currents of Q
1
and Q
2
into nonlinear voltages, which are applied as inputs to block
50
, and to bypass the collector currents of Q
6
and Q
7
to the output of amplifier
20
.
Block
50
(
FIG. 2C
) of prior art amplifier
20
is a compensation circuit for odd-order harmonics. Block
50
includes a second differential pair, consisting of transistors Q
8
and Q
9
, and a resistor R
2
. The bases of transistors Q
8
and Q
9
are respectively connected to the emitters of transistors Q
6
and Q
7
, and the collectors of transistors Q
8
and Q
9
are cross-connected to the output of the amplifier. The purpose of block
50
is to convert voltages appearing at the bases of Q
8
and Q
9
into currents equal to the nonlinear parts of the collector currents of Q
1
and Q
2
. The cancellation of odd-order harmonics is then achieved by cross-connecting of the collectors of Q
8
and Q
9
to the collectors of Q
6
and Q
7
, as shown in FIG.
1
. The structure of amplifier
20
, however, does not provide cancellation of even-order harmonics.
SUMMARY OF THE INVENTION
Preferred embodiments of the present invention provide an improved amplifier circuit, preferably a bipolar linear amplifier, in which second- and third-order harmonics are simultaneously suppressed. The amplifier comprises a main gain unit and a harmonic compensation circuit that remains effective over a range of frequencies and which provides output linearity that generally has low sensitivity to variations in manufacturing processes of the circuit elements. As a result, the amplifier has increased linearity over wider bandwidth than comparable devices known in the art.
In preferred embodiments of the present invention, the linear amplifier comprises an odd order compensation circuit and an even order compensation circuit. These circuits are preferably optimized for the design frequency of the amplifier. Most preferably, the amplifier further comprises a linear phase matching filter, for increasing the effective bandwidth of the compensation circuits.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a differential linear amplifier having an input and an output, including:
a main differential amplification circuit, coupled to receive a differential input signal at the input of the amplifier and to generate a differential output signal at the output of the amplifier;
an odd-order compensation circuit, coupled to sample an odd-order harmonic current in the main differential amplification circuit and to amplify the sampled odd-order harmonic current so as to generate an odd-order compensation signal for subtraction from the differential output signal; and
an even-order compensation circuit, coupled to sample an even-order harmonic current in the main differential amplification circuit and to amplify the sampled even-order harmonic current so as to generate an even-order compensation signal for subtraction from the differential output signal.
In a preferred embodiment, the differential input signal includes an input voltage signal, and the main differential amplification circuit includes a transconductance cell, which is adapted to generate the differential output signal in the form of an output voltage or current signal.
Preferably, the main differential amplification circuit includes a differential pair of transistors mutually connected by a lattice of resistors, the lattice having first and second intermediate nodes, wherein the resistors are arranged to cancel the odd-order harmonic current at the first and second intermediate nodes, and wherein the even-order compensation circuit has first and second inputs that are respectively coupled to the first and second intermediate nodes so as to sample the even-order harmonic current. Most preferably, the even-order compensation circuit includes a pair of transistors, which are coupled respectively to the first and second differential inputs of the even-order compensation circuit, and which are mutually linked by a biasing circuit having a resistance chosen so that the even-order compensation signal cancels a second-order harmonic component in the differential output signal.
Preferably, the amplifier includes a filter, coupled to the output of the amplifier between the main differential amplification circuit and the odd-order compensation circuit, so as to provide phase matching of a third-order harmonic component at a desired frequency at the output of the amplifier between the differential output signal generated by the main differential amplification circuit and the odd-order compensation signal. Most preferably, the filter includes a second-order linear filter. Additionally or alternatively, the filter is further coupled between the main differential amplification circuit and the even-order compensation circuit, so as to provide phase matching of a second-order harmonic component at the desired frequency at the output of the amplifier between the differential output signal generated by the main differential amplification circuit and the even-order compensation signal.
There is also provided, in accordance with a preferred embodiment of the present invention, a differential linear amplifier hav
Bruck Yuri
Burdo Gennady
Zelikson Michael
Browdy and Neimark , P.L.L.C.
International Business Machines - Corporation
Mai Lam T.
Tokar Michael
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