Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
1999-11-12
2002-04-02
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S257000
Reexamination Certificate
active
06366165
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an amplifier comprising an input stage having a pair of inputs for receiving a differential input signal and a pair of outputs for delivering a differential intermediate signal in response to the differential input signal; an intermediate stage for converting the differential intermediate signal to a non-differential intermediate signal, which intermediate stage comprises a current mirror having an input branch and an output branch for receiving the differential intermediate signal; an output stage having an input coupled to the output branch and having an output for delivering an output signal to an output of the amplifier; and means for stabilizing the amplifier.
Such an amplifier is known from the general state of the art as shown in FIG.
1
. The known amplifier has a first reference terminal V
EE
and a second reference terminal V
CC
. A supply voltage source SV for biasing the amplifier is connected between the first reference terminal V
EE
and the second reference terminal V
CC
. The known amplifier further comprises an input stage IP
ST
, an intermediate stage INT
ST
, and an output stage OP
ST
. The input stage IP
ST
comprises a transistor Q
6
and a transistor Q
7
, which are arranged as a differential pair. The bases of the transistors Q
6
and Q
7
are connected to a pair of inputs INN,INI to which a differential input signal V
in
is supplied. The emitters of the transistors Q
6
and Q
7
are connected to a current source I
6
for biasing the differential pair. The differential pair delivers a differential intermediate signal at the collectors CQ
6
and CQ
7
of the transistors Q
6
and Q
7
, respectively. The intermediate stage INT
ST
has an input branch comprising a series arrangement of a resistor R
5
and a transistor Q
5
. The transistor Q
5
is arranged as a diode. The intermediate stage INT
ST
further has an output branch comprising a series arrangement of a resistor R
4
and a transistor Q
4
. The base of the transistor Q
4
is connected to the base of transistor Q
5
. The input branch and the output branch are coupled between the first reference terminal V
EE
and the second reference terminal V
CC
. The input branch and the output branch are biased by current sources I
5
and I
4
, respectively. The output stage OP
ST
comprises a transistor Q
2
having a base coupled to the collector of transistor Q
4
, an emitter coupled to the first reference terminal V
EE
, and a collector coupled to the input of a current mirror Q
3
,Q
13
. The input of the current mirror Q
3
,Q
13
is formed by a diode-connected transistor Q
3
. The output of the current mirror Q
3
,Q
13
is formed by the collector of the transistor Q
13
. The base and emitter of the transistor Q
3
are coupled to the base and the emitter of the transistor Q
3
, respectively. The transistor Q
13
is biased by a current source I
3
. The output stage OP
ST
further comprises a transistor Q
1
, which is biased by a current source I
1
. A base of the transistor Q
1
is coupled to the collector of the transistor Q
13
. A collector of the transistor Q
1
is coupled to the output OP of the amplifier to deliver an output signal V
out
. An emitter of transistor Q
1
is coupled to the first reference terminal V
EE
. Miller capacitors C
M1
and C
M2
for stabilizing the amplifier are coupled between the output OP and the base of transistor Q
1
, and between the output OP and the base of transistor Q
2
, respectively.
The principle of operation of the known amplifier as shown in
FIG. 1
is as follows. The differential pair Q
6
,Q
7
converts the differential input signal V
in
into currents of opposite phases, which are delivered by the collectors CQ
6
and CQ
7
. The intermediate stage INT
ST
converts these currents into a single current, which is delivered by the collector of transistor Q
4
. This single current is then amplified and converted by the output stage OP
ST
in order to deliver the output signal V
out
of the amplifier. In order to obtain a stable amplifier, the amplifier may include only one gain-stage with a so-called dominant pole and it may further include stages with non-dominant poles. If the Miller capacitors C
M1
and C
M2
are disregarded then the amplifier comprises in fact three gain stages, each with a dominant pole. The input stage IP
ST
and the intermediate stage INT
ST
form together a first gain stage with a first dominant pole at the collector of the transistor Q
4
. The transistor Q
2
and the current mirror Q
3
,Q
13
form together a second gain stage with a second dominant pole at the collector of transistor Q
13
. The transistor Q
1
is a third gain stage with a third dominant pole at the output OP. The Miller capacitor C
M1
performs pole splitting, i.e. the third dominant pole becomes non-dominant while the second dominant pole becomes even more dominant. The Miller capacitor C
M2
also performs pole splitting, i.e. the first dominant pole becomes even more dominant while the second dominant pole becomes, in comparison with the first dominant pole, non-dominant. Thus, the amplifier has only one dominant pole at the collector of transistor Q
4
. Therefore, the components of the amplifier can be dimensioned quite easily in order to obtain a stable operation of the amplifier. The Miller compensation technique for stabilizing the amplifier in the manner as shown in
FIG. 1
is known as the nested Miller compensation technique since it comprises a first Miller loop formed by the transistor Q
1
and the Miller capacitor C
M1
, and a second Miller loop formed by the transistor Q
2
, the current mirror Q
3
,Q
13
, and the first Miller loop. Thus, the first Miller loop is nested within the second Miller loop. The function of the current mirror Q
3
,Q
13
is to obtain a correct phase relationship within the second Miller loop.
A problem of the known amplifier is that the current mirror Q
3
,Q
13
must handle a relatively large base current of transistor Q
1
and therefore the transistors Q
3
and Q
13
must have relatively large dimensions. In the quiescent state of the amplifier the current mirror Q
3
,Q
13
is biased by a relatively small current so that the transit frequency of the current mirror Q
3
,Q
13
is relatively low, which adversely influences the maximum bandwidth of the amplifier.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an improved amplifier with an extended bandwidth.
To this end, according to the invention, the amplifier of the type defined in the opening paragraph is characterized in that the means for stabilizing the amplifier include a capacitor coupled between the output of the amplifier and the input branch.
The invention is based on the insight that the current mirror already available within the intermediate stage INT
ST
can also be used in a respective Miller loop to stabilize the amplifier as an alternative to the above-mentioned second Miller loop without causing a wrong phase relationship in the respective Miller loop. As a consequence, the current mirror Q
3
,Q
13
is not necessary in the respective Miller loop. Therefore, the maximum bandwidth of the amplifier is extended.
In the general state of the art another solution is known for the above-mentioned problem caused by the current mirror Q
3
,Q
13
. The solution is the use of a differential stage in the output stage OP
ST
instead of the transistor Q
2
and the current mirror Q
3
,Q
13
. This solution, however, causes another problem: the differential stage cannot function properly at a low supply voltage. The amplifier according to the invention does not have a differential stage in the output stage OP
ST
. Therefore, the amplifier according to the invention has a large bandwidth and can also function properly at a low supply voltage.
Further advantageous embodiments of the inventions are specified in claims
2
-
8
.
REFERENCES:
patent: 4194136 (1980-03-01), Butler
patent: 5952882 (1999-09-01), Kolluri
patent: 5966050 (1999-10-01), Yoshino et al.
patent: 6084475 (2000-07-01), Rincon-Mora
De Langen Klaas-Jan
Huijsing Johan H.
Choe Henry
Pascal Robert
U.S. Philips Corporation
Vodopia John F.
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