Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-08-29
2003-06-17
Nguyen, Patricia (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S292000, C330S294000
Reexamination Certificate
active
06580325
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to frequency compensated amplifiers, and in particular, to amplifier circuits with Miller-effect frequency compensation.
2. Description of the Related Art
Miller feedback is commonly used to compensate multistage amplifiers. By adding a feedback capacitance around an intermediate amplifier stage phase compensation is provided by introducing a pole-zero cancellation. As is well known, due to the Miller effect, a response zero is developed in the amplifier stage having the feedback capacitance such that the response zero is coincident with the pole of the succeeding amplifier stage.
A drawback of Miller feedback is a poor power supply rejection ratio (PSRR). At high frequency, standard Miller feedback causes the PSRR to begin to degrade at the dominant pole frequency. This can be improved, as shown by Ribner and Copeland in “Design Techniques for Cascoded CMOS Op Amps With Improved PSRR and Common Mode Input Range”, IEEE JSSCC December 1984 (Ribner et al., incorporated herein by reference), by feeding the Miller capacitance back to a low impedance node. This method provides a significant improvement to the PSRR. However, it also creates two complex poles at high frequency that often cause the amplifier to be unstable.
Referring to
FIG. 1
, a folded cascode amplifier has been proposed using a modified Miller feedback as described by Ribner et al. Capacitor C
2
is traditionally used to compensate the Miller loop. For the following discussion, it is assumed that capacitor C
2
is significantly larger than the gate-to-source capacitance C
GS
of transistor M
4
. In cases where this is not true, a low input capacitance buffer (not shown), such as a source follower, can be connected between node N
1
and the gate terminal of transistor M
4
to reduce the capacitive loading on the high impedance node N
1
by transistor M
4
. (In the Figures and throughout the following discussion, transistors M
1
, M
2
, M
3
, M
4
, M
5
, M
6
, M
7
, M
8
are insulated gate field effect transistors, such as P-type and N-type metal oxide semiconductor field effect transistors (P-MOSFETs and N-MOSFETs), and are depicted using conventional transistor symbols for P-MOSFETs and N-MOSFETs.)
Referring to
FIGS. 2 and 3
, there are two loops in the system that need to be analyzed. The first is the traditional DC loop as depicted in FIG.
2
. The loop characteristics of this DC system are well known in the art and, therefore, need not be analyzed here. The second is the Miller feedback loop as depicted in FIG.
3
. As is well known, when analyzing the Miller loop, the inputs to the DC loop are AC grounded. In this way, the characteristics of the Miller loop can be determined independently of the DC loop. Capacitor C
1
creates a zero at DC and a dominant pole due to the high impedance of node V
3
reflected through transistor M
1
. The Miller loop also has two low frequency poles at nodes V
3
and Vout due to capacitors C
2
and C
1
. It is these two poles that converge when the Miller loop is closed, thus giving rise to a pair of complex poles in the DC loop. Eliminating one of these poles would significantly improve the loops' stability.
Referring to
FIG. 4
, the Miller loop can be simplified as shown. Referring to
FIG. 5
, this circuit can be modeled to a first order as shown. For simplicity, the capacitance of capacitor C
1
is set to A times the capacitance of capacitor C
2
(Equation 0). The loop transmission can be characterized by Equation 1. As expected, the cascode portion of the loop contributes a DC zero, and two poles, while the output stage contributes a single pole as expressed by Equation 2.
c
1
&khgr;AC
2
&khgr;AC
Equation 0:
Equation
1
:
V
o
V
i
=
[
(
sAC
(
gds
1
+
gm
1
+
gmb
1
)
)
(
(
gds
2
+
gds
1
+
sC
)
(
gds
3
+
gds
1
+
gm
1
+
gmb
1
+
sAC
)
-
(
gds
1
)
(
gds
1
+
gm
1
+
gmb
1
)
)
]
&AutoLeftMatch;
[
-
gm
4
gds
4
+
s
(
AC
)
]
Equation
2
:
ω
p3
≈
gds
4
AC
Finding the poles of the cascoded stage is somewhat more involved. Using the standard form for solving the roots of a second order equation produces Equations 3-9. Equation 10 is presented as a compact expression for the total Miller loop system response.
Equation
3
:
r
=
-
b
±
b
2
-
4
ac
2
a
b
2
&khgr;gds
1
AC+
2
gds
1
(
gds
3
+gds
1
+gm
1
+gmb
1
)
AC
2
+(
(gds
3
+gds
1
+gm
1
+gmb
1
)
2
C
2
Equation 4:
4
ac&khgr;
4
AC
2
(
gds
2
gds
3
+gds
2
gds
1
+gds
2
(
gm
1
+gmb
1
)+
gds
3
gds
1
) Equation 5:
b
=(
gds
1
AC+
(
gds
3
+gds
1
+gm
1
+gmb
1
)
C
) Equation 6:
2
a=
2
AC
2
Equation 7:
Equation
8
:
ω
p1
=
(
gds
1
AC
+
(
gds
3
+
gds
1
+
gm
1
+
gmb
1
)
C
)
2
AC
2
-
gds
1
AC
+
2
gds
1
(
gds
3
+
gds
1
+
gm
1
+
gmb
1
)
AC
2
+
(
gds
3
+
gds
1
+
gm
1
+
gmb
1
)
2
C
2
-
4
AC
2
(
gds
2
gds
3
+
gds
2
gds
1
+
gds
2
(
gm
1
+
gmb
1
)
+
gds
3
gds
1
)
(
2
AC
2
)
Equation
9
:
ω
p1
=
(
gds
1
AC
+
(
gds
3
+
gds
1
+
gm
1
+
gmb
1
)
C
)
2
AC
2
+
gds
1
AC
+
2
gds
1
(
gds
3
+
gds
1
+
gm
1
+
gmb
1
)
AC
2
+
(
gds
3
+
gds
1
+
gm
1
+
gmb
1
)
2
C
2
-
4
AC
2
(
gds
2
gds
3
+
gds
2
gds
1
+
gds
2
(
gm
1
+
gmb
1
)
+
gds
3
gds
1
)
(
2
AC
2
)
Equation
10
:
V
o
V
i
=
[
(
gds
1
+
gm
1
+
gmb
1
)
(
-
gm
4
)
gds
4
]
&AutoLeftMatch;
[
sAC
(
1
+
s
ω
p1
)
(
1
+
s
ω
p2
)
]
[
1
1
+
s
ω
p3
]
The pole at frequency &ohgr;
p1
can be shown to be much lower than the pole at frequency &ohgr;
p2
and thus of little interest for purposes of this analysis since it is effectively canceled by the zero at DC. Using the assumption expressed by Equation 11 and for moderately low values of the factor A, the expression for the pole at frequency &ohgr;
p2
can be simplified as shown in Equation 12.
gm≈
10
gmbs≈
100
gds
Equation 11:
Equation
12
:
ω
p2
≈
b
a
≈
(
gds
1
AC
+
(
gds
3
+
gds
1
+
gm
1
+
gmb
1
)
C
)
AC
2
≈
(
gds
1
AC
+
(
gm
1
+
gmb
1
)
C
)
AC
2
≈
gm
1
+
gmb
1
AC
≈
gm
1
AC
Referring to
FIGS. 6-9
, the open loop frequency responses for two nodes in the circuit of
FIG. 5
are produced.
FIG. 6
depicts the magnitude response as seen from node voltage Vi to node voltage V
3
, while
FIG. 7
depicts the phase response. From this it can be seen that the pole at frequency &ohgr;
p2
has already degraded the phase margin by 90 degrees. If the pole at the output is sufficiently low, the system will be unstable and exhibit peaking at the unity gain frequency.
FIG. 8
depicts the open loop magnitude response from node voltage Vi to node voltage Vo. From this it can be seen that the output pole causes the high frequency rolloff to degrade with two poles before the unity gain frequency.
FIG. 8
also depicts the closed loop magnitude response.
FIG. 9
depicts the open and closed loop phase response from which it is evident that the phase margin is nearly zero. Therefore, the Miller loop is unstable and will cause severe peaking when inserted in the DC loop.
While the DC loop is not analyzed here in detail, a brief explanation of the effect of the Miller loop can be provided.
National Semiconductor Corporation
Nguyen Patricia
Wildman Harrold Allen & Dixon
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