Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
1999-10-28
2001-08-28
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S263000
Reexamination Certificate
active
06281752
ABSTRACT:
This invention refers to an amplifier with improved, high precision, high speed and low power consumption architecture, particularly suitable for a lot of applications.
BACKGROUND OF THE INVENTION
It is well known, in the field of analog electronics, that implementation of systems meeting requirements where high precision, low power consumption and high sped are simultaneous required is more and more requested. The main problem is to balance such requirements that, according to the known techniques, are in conflict with each other. Therefore, designers are forced to find the best trade off for their specific application.
The requirements which designers should try to meet may be resumed as:
DC precision (Low Input Offset Voltage, Vos, and Input Offset Currents, Ios, and Low Bias Currents, Ib);
AC precision (Low Noise, Wide Power-Bandwidth and Low Distortion);
High speed and Wide dynamic range;
Low power consumption
The main object of this invention is to provide innovative solutions, which substantially mitigate existing problems and can be applied to both voltage feedback and current feedback architectures.
PRIOR ART AND RELATED PROBLEMS
It is first of all to take into account the present prior art, related to amplifier architectures and their constraints.
The main characteristics of conventional architectures, which make use of class A or AB operation in the input stage and of class A operation in the intermediate stage, can be examined by referring to
FIG. 1
of the annexed drawings, where the simplified block diagram of a conventional voltage-feedback operational amplifier is shown.
The input stage is a differential voltage to current converter, wherein
g
m
=(
I
R
−I
L
)/(
V
1
−V
2
)
is the transconductance and V
os
′ is the offset voltage of the input stage. The current available from the input stage is limited to I
B
by the bias network, for class A operated input stages and is much higher than I
B
for class AB operated input stages.
The intermediate stage is a high-gain current amplifier, the output of which is given by
I
N
=G
D
(
I
R
−I
L
)+
I
os
where G
D
→∞, and Ios is the intermediate stage output offset current. Therefore, the output voltage is given by
V
o
=V
o
′=[I
Q
−G
D
(
I
R
−I
L
)−
I
os
]R
i
.
It is worth noting that this scheme shows remarkable feature that the operating point of the intermediate stage, being V
o
dependent on I
PO
=I
Q
, which in this context acts as a reference current, is forced to I
NO
=I
PO
=I
Q
when feedback loop is closed around the amplifier. Therefore, regardless of the actual value of G
D
, the operating point is very stable.
The output stage is usually a complementary common collector class AB stage (generally G
O
=1) which is capable of providing peak output currents well in excess of the quiescent current.
V
OS
(O) is the offset voltage of the output stage.
C
o
is the frequency compensation capacitance, which sets the dominant pole and the phase margin of the amplifier, and R
i
//C
i
is the combination of the output impedance of the intermediate stage and the input impedance of the output stage.
In this amplifier, output voltage is given by
V
O
=(
V
1
−V
2
)·
A
OL
+V
OST
(1)
where
A
OL
=g
m
G
D
Ri
(2)
is the DC open loop gain, and
V
OST
=A
OL
V
OS
(
i
)+
I
OS
Ri+V
OS
(
o
) (3)
is the total output offset voltage, while the input offset voltage V
OS
is the one given by the total offset output voltage, divided by the open loop gain, that is
V
OS
=
V
OST
A
OL
=
V
OS
(
i
)
+
I
OS
g
m
G
D
+
V
OS
(
O
)
g
m
G
D
Ri
(
4
)
Since in this architecture G
D
→∞, the contribution to the offset of the intermediate and output stage is virtually null and equation (4) becomes:
V
OS
≈V
OS
(
i
) (5)
Furthermore, unity gain frequency for small signals in the same amplifier is given by
f
T
=g
m
/2&pgr;
C
o
(6)
while maximum speed is given by the slew-rate limit SR=dV
o
/dt=dV
o
′/dt, which is set by the maximum current available to charge and discharge node B capacitances found in the amplifier.
Therefore, considering again the architecture of FIG.
1
and neglecting the current through R
i
, the maximum limit of rising edge slew-rate SRB(r) at node B is equal to
SR
B
(
r
)=
I
P
/(
C
o
+C
i
)=
I
Q
/(
C
o
+C
i
) (7)
since the current available is I
P
=I
PO
=I
Q
. For this to be true, it is necessary that the current flowing through C
o
from node B, which equals I
co
=I
P
C
o
/(C
o
+C
i
) is sustained at node B by the input stage. Since the current available at node A is I
B
, then it is necessary that
I
B
≧I
P
C
o
/(
C
o
+C
i
) (8)
Inequality (8) is not usually satisfied, since the bias current I
B
has to be limited to few milliamps for reasons of noise performance, dc precision and frequency stability (since gm is proportional to I
B
). Therefore the maximum limit of rising edge slew rate will be given by
SR
B
(
r
)=
I
B
/C
o
(7A)
With the same assumption, since the current available at node B for discharging all node capacitances is only limited by the gain of the intermediate stage, which for assumption is very high, i.e. G
D
→∞, the maximum limit of falling edge slew-rate SR
B
(f) at node B still depends on the current available at node B for discharging C
o
, so that one can finally write
SR
B
(
f
)≈
SR
B
(
r
)=(
I
B
)/(
C
o
) (9)
which represents the main limit to the slew-rate for class A input stages.
Resuming, the advantages of conventional amplifier architectures of
FIG. 1
, may be summarised as a high DC open loop gain, a low noise and a high DC precision; the disadvantages as poor slew-rate performances, which are determined by the class A input stage, then in the poor width of power band, wherein f
max
=SR/2V
peak
.
For instance:
I
B
=0.5 mA, I
P
=2 mA, C
o
=30 pF, Ci=10 pF, Ri=100 k, gm=0.001 Vos(i)=1 mV, Ios=0.1 mA, Vos(o)=5 mV
Then eq. (4) yields about Vos=1 mV, while eq. (6) and (8) yield 50 V/&mgr;s and 16.6 V/&mgr;s, respectively.
This example shows that dc precision of the amplifier, as well as its speed, strongly depend on the performance of the input stage.
Solutions to the problem of speed limitation, which is typical of class A architectures, are already known. This problem is normally dealt with according to two different choices of architecture: 1) Amplifier architecture with class AB input stage and class A intermediate stage; 2) Amplifier architecture with all class AB stages.
In the first case, an effective means of overcoming the problem of the limit set by ep. (9) is available, since in class AB input stages the available peak output current, I
i(max)
, is much higher than the total bias current I
B
. Indeed:
SR
B
(
r
)=
I
Q
/(
C
o
+C
i
) (10)
SR
B
(
f
)=
I
i(max)
/(
C
o
) (11)
As a result the situation is such that SR
B
(f)>SR
B
(r), and the slew-rate limit in these architectures is set by the class A intermediate stage. Slew rate can be increased only by increasing I
P
=I
PO
=I
Q
proportionally, but there is a practical limit set by power consumption and dc-ac precision requirements.
A higher slew-rate than in the basic architecture is thus obtained, but with a lower DC and AC precision, due to the increased complexity of the input class AB stages.
The most robust and used configuration shown in FIG.
2
A and derived from circuit techniques well established in current-feedback amplifier architectures, corresponds to the second case, which is a must when a high value of slew rate is necessary. Here, the most important thing to notice is the use of two low current gain complementary halves (usually unit gain current mirrors) in the intermediate stage.
Nguyen Khanh Van
Nixon & Vanderhye PC
Pascal Robert
Telefonaktiebolaget LM Ericsson
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