Amplifiers – With semiconductor amplifying device – Including protection means
Reexamination Certificate
2002-12-17
2004-08-10
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including protection means
C330S288000, C330S20700P
Reexamination Certificate
active
06774726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to amplifiers having at least three stages and the output stage of which is formed by a MOS transistor. The present invention relates, for example, to amplifiers used to amplify audio signals.
2. Description of the Related Art
FIG. 1
shows an example of an architecture of an amplifier including first
11
, second
16
, and third
18
stages. The first stage
11
has two input terminals
12
,
13
across which a differential voltage V
DIFF
is applied. Output
14
of first stage
11
is applied to an input
15
of second stage
16
. Output
17
of second stage
16
is applied to the gate of a MOS output transistor
18
which forms the third stage of amplifier
10
. As an example, output MOS transistor
18
is of type P. The source of output transistor
18
is connected to a first voltage source Vdd. The drain of output transistor
18
is connected to a second voltage source, for example, ground GND, via a D.C. bias current source
19
. Drain current I
D1
, voltage V
DS1
between the drain and the source, and voltage V
GS1
between the gate and the source have also been indicated for output MOS transistor
18
.
A first capacitor
22
connects the drain of output transistor
18
to input
15
of second stage
16
. A second capacitor
23
connects the drain of output transistor
18
to output
17
of second stage
16
.
An output terminal
24
of amplifier
10
corresponds to the drain of output transistor
18
.
A load, including for example a resistor
25
coupled in parallel with a capacitor
26
, is connected between output terminal
24
and ground GND with an interposed coupling capacitor
27
.
FIG. 2
illustrates, in a logarithmic representation, the simplified shapes of curve
30
of gain G and of curve
31
of phase &phgr; of the open-loop response of amplifier
10
of
FIG. 1
according to frequency.
As appears on curve
30
, gain G exhibits three cut-off frequencies f
1
, f
2
, and f
3
. From the low frequencies to first cut-off frequency f
1
, the gain is substantially constant and equal to a value G
0
. Between first f
1
and second f
2
cut-off frequencies, gain G exhibits an attenuation of approximately −20 dB/decade. Between the second f
2
and third f
3
cut-off frequencies, gain G exhibits an attenuation of approximately −40 dB/decade. Finally, beyond third cut-off frequency f
3
, gain G exhibits an attenuation of approximately −60 dB/decade. Cut-off frequencies f
1
, f
2
, and f
3
are respectively associated with first
11
, second
16
, and third
18
stages.
Phase &phgr; of amplifier
10
which corresponds to the phase-shift between the signal at output terminal
24
and differential voltage V
DIFF
is on the order of 180° at low frequencies and decreases by 90° in the vicinity of each cut-off frequency.
Cut-off frequencies f
2
and f
3
are given by the following expressions:
f
2
=g
m2
*g
m3
*(
R
L
//r
ds
)/[1
+g
m3
*(
R
L
//r
ds
)]*2
&pgr;* C
2
(1)
f
3
=g
m3
/(2
&pgr;*C
L
) (2)
where g
m2
is the transconductance of second stage
16
, g
m3
is the transconductance of third stage
18
, r
ds
is the value of the equivalent resistance of output transistor
18
between the drain and the source, R
L
is the value of resistor
25
of the load, C
2
is the capacitance of capacitor
23
, and C
L
is the capacitance of capacitor
26
of the load. Expression r
ds
//R
L
corresponds to the value of the resistance equivalent to resistances R
L
and r
ds
placed in parallel and is equal to r
ds
*R
L
/(r
ds
+R
L
).
In equation (1), when term (g
m3
*(R
L
//r
ds
) is very large as compared to one, the expression of cut-off frequency f
2
simplifies and the following expression is obtained:
f
2
=g
m2
/(2
&pgr;*C
2
) (3)
A frequency, called the gain-bandwidth product frequency PGB, which corresponds to the frequency at which the gain is equal to one (that is, equal to zero in decibel) is usually defined. The expression of frequency PGB is the following:
PGB=g
m1
*g
m2
g
m3
R
L
*R
eq
/2&pgr;*
C
1
*(
g
m2
*g
m3
*R
L
* R
eq
+1) (4)
where g
m1
is the transconductance of the first stage, C
1
is the capacitance of capacitor
22
, and R
eq
is the value of the equivalent resistance seen from the output of second stage
16
of amplifier
10
. In the case where term g
m2
*g
m3
*R
eq
*R
L
is very large as compared to one, the expression of frequency PGB simplifies, which then provides:
PGB=g
m1
/(2
&pgr;*C
1
) (5)
For some values of differential voltage V
DIFF
, amplifier
10
may have a so-called unsteady operation. An unsteadiness of amplifier
10
may translate as the development of parasitic oscillations on the output signal.
A condition to ensure the steadiness of this type of amplifier is that phase &phgr; at frequency PGB, also called the phase margin M
&phgr;
, is positive and, usually, greater than 30 degrees. For this purpose, it is desired to obtain cut-off frequencies such that cut-off frequency f
3
is greater than cut-off frequency f
2
, usually, at least twice as large, and that cut-off frequency f
2
is greater than frequency PGB, usually at least twice as large. This enables ensuring the obtaining of a positive phase margin M
&phgr;
.
FIG. 3
shows curves
35
A,
35
B representative of current I
D1
of the drain of output transistor
18
according to the opposite of voltage V
DS1
for two different values of voltage V
GS1
, noted V
GS1
′ and V
GS1
″. MOS transistor
18
being of type P, the gate-source voltage is negative and V
GS1
′ is smaller than V
GS1
″.
Each curve
35
A,
35
B includes a first region
36
A,
36
B, called the linear or ohmic region, in which drain current I
D1
strongly varies, substantially proportionally to drain-source voltage V
DS1
. The equivalent resistance of the transistor between the drain and the source in the linear region is called r
on
. Resistor r
on
corresponds to the inverse of the slope of curve
36
A,
36
B in the linear region. Resistance r
on
varies according to V
GS1
.
Each curve
35
A and
35
B includes a second region
37
A,
37
B, called the saturated region or constant drain current region, in which drain current I
D1
varies very slightly and substantially proportionally to drain-source voltage V
DS1
. The equivalent resistance between the drain and the source in the saturated region is called R
0
. Resistance R
0
corresponds to the inverse of the slope of curve
35
A,
35
B in saturated region
37
A,
37
B. Resistance R
0
varies little according to V
GS1
.
Conventionally, resistance R
0
is much higher than resistance r
on
. As an example, r
on
may be on the order of 10 ohms and R
0
may be on the order of from some ten to some hundred kiloohms.
In a normal operating mode of amplifier
10
, output transistor
18
is in the saturated region. In this case, the value of resistance r
ds
appearing in the expression of cut-off frequency f
2
is equal to resistance R
0
. Term g
m3
*(R
L
//r
ds
) is then very large as compared to one, and the simplified expression of cut-off frequency f
2
, given by equation (3), is valid.
However, in some operating modes of amplifier
10
, in particular for high values of drain current I
D1
(which corresponds to negative voltages V
GS1
of high absolute values), output transistor
18
may switch from the saturated state to the linear state.
To illustrate this phenomenon, a load line
39
for a given load resistance has been shown in FIG.
3
. The operating point of the circuit formed by the amplifier and the load corresponds to an interception between curve
39
and the curve representative of drain current I
D1
according to drain-source voltage V
DS1
.
It can also be noted that, when the gate-source voltage is equal to V
GS1
′, operating point
40
B is located in saturated portion
37
B of curve
35
B. In this case, resistance r
ds
is equal to R
0
and the simplified expression, given by equation (2), of cut-off frequency f
2
is valid.
Wh
Goutti Frederic
Rabary Vincent
Choe Henry
de Guzman Dennis M.
Seed IP Law Group PLLC
STMicroelectronics S.A.
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