Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-03-25
2003-01-14
Nguyen, Patricia (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
Reexamination Certificate
active
06507245
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an amplifying circuit of an amplifier, and more particularly, to an amplifier which is driven in a complementary manner using a common source amplifying circuit to extend the input and output signal voltage range.
2. Description of the Prior Art
The rapid growth of technology has insured that electronic signals will remain an important medium for transmitting data. Signals are used to control various servers, mechanical devices, and electrical apparatus. They allow people to control many fast and labor-saving machines, adding convenience to modern life. Of course, electronic signals are also an indispensable medium for data transmission. Things we often take for granted, such as mobile phones, radio, television, and satellite communications, all rely on electronic signals.
Good circuit design is indispensable for processing these electronic signals and amplifiers are often foundation blocks for circuits. Base functions of an amplifier are to amplify or magnify the signal, and to provide buffering and driving capability. Although the electric driving ability (including current and/or voltage) of the electronic signal is not large, the amplifier can be driven and also generate output signals which have a larger electric driving ability, or current strength, and maintain the same waveform as the input signals.
Please refer to FIG.
1
.
FIG. 1
is a functional block diagram of a prior art amplifier
10
. The amplifier
10
comprises an input circuit
12
, an output circuit
14
, and a unit-gain buffer circuit
18
connected between the input circuit
12
and the output circuit
14
. The input circuit
12
is used to receive signals transmitted from an external circuit (not shown in FIG.
1
). After the signals have passed through the input circuit
12
, the signals travel to an input end of the unit-gain buffer circuit
18
. The input end is connected to a node A. The unit-gain buffer circuit
18
will not amplify voltage amplitude of the signals (so it is unit-gain), but it can provide an input signal buffer and increase the strength of the current. That means, although the current driving ability of the signals transmitted into the unit-gain buffer circuit
18
is not large, the unit-gain buffer circuit
18
can be driven and also generate output signals which have a larger current while having the same voltage amplitude as the input signals. The output signals transmit to the output circuit
14
through a node B. The output circuit
14
can further amplify the signals, and provide good output impedance.
A typical unit-gain buffer circuit is composed of an operational amplifier and a suitable negative feedback circuit. The unit-gain buffer circuit
18
shown in
FIG. 1
uses the operational amplifier
16
to be a main portion of the unit-gain buffer circuit
18
. The operational amplifier
16
has two differential input ends; one of the input ends is connected to node A, and another input end is connected to an output end of the operational amplifier in node B through an electrical path
19
, forming the negative feedback circuit.
In theory, the voltage waveform of the signals on node B (the output end of the unit-gain buffer circuit
18
) is the same as the voltage waveform of the signals on node A (the input end of the unit-gain buffer circuit
18
), achieving a result of unit-gain. The functional relationship between the input signal voltage and the output signal voltage in an ideal unit-gain buffer circuit is perfectly linear. However, this is not possible in the real world. Because the operational amplifier has certain output voltage swing limitations, the output signal voltage of the unit-gain buffer circuit also has certain voltage swing limitations. Particularly, when the input signal voltage of the unit-gain buffer circuit becomes small (near zero voltage), because of the lower limit of the voltage range of the output signal, the output signal voltage of the unit-gain buffer circuit is unable to follow the low input signal voltage. Therefore, the error between the output signal voltage and the input signal voltage will increase, and the unit-gain buffer circuit cannot achieve the function of unit-gain. Similarly, when the input signal voltage of the unit-gain buffer circuit becomes large, near current bias of the amplifier, because of the upper limit of the voltage range of the output signal, the output signal voltage of the unit-gain buffer circuit is also unable to follow the input signal voltage. Therefore, the unit-gain buffer circuit cannot achieve the ideal unit-gain standard.
For a further description of the limitations of the output signal voltage range of an actual unit-gain buffer circuit, please refer to FIG.
2
.
FIG. 2
is a perspective view of an amplifying circuit
20
according to a prior art. Besides a typical input circuit
22
and an output circuit
24
, the amplifying circuit
20
uses a gain circuit
26
to be the unit-gain buffer circuit. VDD is used for biasing the gain circuit
26
. The gain circuit
26
comprises a first differential pair
28
, a second differential pair
30
, a first driving circuit
32
and a second driving circuit
34
. Two differential ends of the first differential pair
28
are connected to nodes NN
1
and NN
2
. Two differential ends of the second differential pair
30
are also connected to nodes NN
1
and NN
2
. The first differential pair
28
is connected to the first driving circuit
32
on nodes NN
4
and NN
5
in a cascade manner. The second differential pair
30
is also connected to the second driving circuit
34
on nodes NN
6
and NN
7
in a cascade manner. The first driving circuit
32
is connected to the second driving circuit
34
on nodes NN
8
and NN
3
. Node NN
3
is used as an output end of the gain circuit
26
. Nodes NN
1
and NN
2
are used as two differential input ends of the operational amplifier. Node NN
1
is an input end of the gain circuit
26
. Node NN
2
is connected to node NN
3
through path
29
, forming a negative feedback circuit and making the gain circuit
26
a unit-gain buffer circuit.
In the gain circuit
26
, the first differential pair
28
comprises two n-type MOS (metal-oxide semiconductor) transistors M
1
and M
2
. The first differential pair
28
is biased by current source Iss
1
. The second differential pair
30
comprises two p-type MOS transistors MP
1
and MP
2
. The second differential pair
30
is biased by current source Iss
2
. Two output ends of the first differential pair
28
are connected to nodes NN
4
and NN
5
, and use transistors M
9
and M
10
to be active load. Gates of transistors M
9
and M
10
use direct current voltage Vg
4
to bias. The transistors M
9
and M
10
are used as a current source. Gates of the two transistors M
3
and M
4
in the first driving circuit
32
use direct current voltage Vg
3
to bias, making the transistors M
3
and M
4
function as a common-gate amplifier. Similarly, in the second driving circuit
34
, the transistors M
5
and M
6
, biased by direct current voltage Vg
2
, are also used as a common-gate amplifier. The transistors M
7
and M
8
form a current mirror for biasing and to be active load.
The operation of the prior art gain circuit
26
can be described as follows. The nodes NN
1
and NN
2
can be treated as two differential input ends of the first differential pair
28
and the second differential pair
30
. The signals inputted into the two differential input ends of the first differential pair
28
will output to the active load M
9
and M
10
through nodes NN
4
and NN
5
, and be amplified by transistors M
3
and M
4
that are common-gate amplifiers. Then the signals will be outputted to nodes NN
8
and NN
3
. On the other side, the signals inputted into the two differential input ends of the second differential pair
30
will be outputted to nodes NN
6
and NN
7
. The transistors M
7
and M
8
that form the current mirror, can couple the signals (including the contribution of the transistors M
3
and M
5
of the common-gat
AMIC Technology (Taiwan) Inc.
Hsu Winston
Nguyen Patricia
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