Amplifier stage having compensation for NPN, PNP beta mismatch a

Amplifiers – With semiconductor amplifying device – Including combined diverse-type semiconductor device

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330255, 330257, 330261, 330263, H03F 330

Patent

active

055128599

ABSTRACT:
A fully symmetrical class AB amplifier includes two controllable current sources in the input stage to compensate for NPN, PNP transistor beta mismatch. This beta mismatch creates an offset current that is reflected back to the input stage and creates a systematic voltage offset. One controllable current source is provided for each of the top side and the bottom side of the input stage, and each current source, sources/sinks a current of a predetermined value to make up the current offset caused by the beta mismatch. In a second embodiment, slew-enhancement transistors are included in an amplifier input stage, one transistor associated with each of the top side and bottom side portions of the stage to provide a current boost during high slew events (transients) at the amplifier non-inverting input. These slew enhancement transistors are normally off; during a fast rising or falling input signal pulse, one of these transistors provides extra base current to the base of the top side or bottom side output transistor of the stage. Additionally, the collector current of each slew enhancement transistor is mirrored back to a high impedance point in an output stage of the amplifier to charge and discharge the compensation and parasitic capacitance during large input signal slews, to further improve amplifier performance.

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U.S. Pending Patent Application Serial No. 08/341,818, filed Nov. 18, 1994, Title: Fast Slewing Amplifier Using Dynamic Current Mirrorw, Attorney Dock No. NS-2599 US.
U.S. Pending Patent Application Serial No.: 08/362,030, filed Dec. 22, 1994, Title: Triple Buffered Amplifier Output Stage, Attorney Docket No. NS-2607 US.

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