Amplifiers – With semiconductor amplifying device – Including differential amplifier
Patent
1988-06-23
1990-06-12
Mullins, James B.
Amplifiers
With semiconductor amplifying device
Including differential amplifier
330265, 330267, H03F 330
Patent
active
049336452
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to an amplifier having a constant-current bias circuit. The amplifier comprises an input stage, a voltage amplified stage having first and second relay terminals and a SEPP output stage having at least one pair of complementary transistors. A bypass current, which is obtained by subtracting a control current flowing between bases of the transistors of the output stage from the current supplied to the first and second relay output terminals, is absorbed by a constant-current element or a constant-current circuit. Alternatively, the voltage appearing between two resistors each directly connected to an output terminal is integrated and then negatively fed back to a voltage-controlled constant-current bias circuit which absorbs the bypass current, thereby to determine the bias of the SEPP output stage.
BACKGROUND OF THE INVENTION
A conventional amplifier comprises, as shown in FIG. 1 for example, an input stage 10, a voltage amplified stage 20 and a SEPP (Single Ended Push-Pull) output stage 30.
The input stage 10 includes a pair of FETs 11 and 12 of monolithic IC, an input terminal 13 connected to the gate of FET 11, an input resistor 14 connected between input terminal 13 and the ground, a resistor 15 connected between the common source of FETs 11 and 12 and a negative power supply -Vcc, and resistors 16 and 17 which are connected between a positive power supply +Vcc and the respective drain of FETs 11 and 12. The gate of FET 12 to the ground and the output terminal are connected negative feedback resistors 18 and 19 which determine the gain or amplification factor of the amplifier.
The voltage amplified stage 20 includes a PNP transistor 21 having a base connected to the drain of FET 11, a PNP transistor 22 having a base connected to the drain of FET 12, a resistor 23 connected between the common emitter of PNP transistors 21 and 22 and the positive power supply +Vcc, an NPN transistor 24 having a collector and a base which are connected to the collector of PNP transistor 22, and an NPN transistor 25 having a base connected to the collector of PNP transistor 22. These NPN transistors 24 and 25 have emitters each connected to the negative power supply -Vcc. The absolute value of the collector current of PNP transistor 22 is substantially equal to that of NPN transistor 25. The collector of PNP transistor 22 provides a first relay output terminal I.sub.1 while the collector of NPN transistor 25 provides a second relay output terminal I.sub.2.
The SEPP output stage 30 has Darlington-connected NPN transistors 31 and 32 each having a collector connected to the positive power supply +Vcc, Darlington-connected PNP transistors 33 and 34 each having a collector connected to the negative power supply -Vcc, an output terminal 35, a first resistor 36 directly connected to output terminal 35 and connected to the emitter of NPN transistor 32, and a second resistor 37 directly connected to output terminal 35 and connected to the emitter of PNP transistor 34. The junction between the emitter of NPN transistor 31 and the base of NPN transistor 32 is connected to output terminal 35 via resistor 38, while the junction between the emitter of PNP transistor 33 and the base of PNP transistor 34 is connected to output terminal 35 via resistor 39. The constant-voltage bias (CVB) circuit 26 is connected between first relay output terminal I.sub.1 connected to the base (first control end) of NPN transistor 31 and second relay output terminal I.sub.2 connected to the base (second control end) of PNP transistor 33.
The bias circuit 26 includes a temperature-compensation NPN transistor 27 having a collector connected to the base of NPN transistor 31 and an emitter connected to the base of PNP transistor 32, a variable resistor 28 connected between the bases of NPN transistors 31 and 27, and a fixed resistor 29 connected between the bases of NPN transistor 27 and PNP transistor 33. The idle current flowing between collectors of NPN transistor 32 and PNP transistor 34 is regulated
REFERENCES:
patent: 3536958 (1970-10-01), Sondermeyer
patent: 4331930 (1982-05-01), Shibata et al.
patent: 4366447 (1982-12-01), Sugiyama
patent: 4384261 (1983-05-01), Yokoyama
Journal of the Audio Engineering Society, vol. 30 (1982), May, No. 5, New York, U.S.A.
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