Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-07-12
2004-11-30
Lam, Tuan T. (Department: 2816)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S254000, C330S258000, C327S052000
Reexamination Certificate
active
06825721
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to high-speed CMOS operational amplifiers, and particularly to gain boost circuitry that increases amplifier gain without increasing noise and without increasing amplifier instability.
The closest prior art is thought to be represented by commonly assigned U.S. Pat. No. 6,150,883 issued Nov. 21, 2000 to Ivanov and U.S. Pat. No. 6,356,153 issued Mar. 12, 2002 to Ivanov et al., both incorporated herein by reference, disclose prior gain boost circuitry. Also, see “The CMOS Gain-Boosting Technique” by K. Bult and G. Geelan in “Analog Integrated Circuits and Signal Processing”, Volume I, pp 119-135 (1981).
A variety of CMOS current mirror circuits are generally known in art, particularly the current mirror which is incorporated within the single stage CMOS amplifier
40
A shown in FIG.
3
. That prior art current mirror includes P-channel transistors
4
and
5
and amplifier
16
. However, the prior art does not disclose use of that current mirror as a gain boost circuit in a CMOS differential amplifier as shown in FIG.
3
.
FIG. 1A
shows a conventional CMOS differential amplifier input stage
1
A including two differentially connected P-channel input transistors
2
and
3
having their sources connected to a tail current source
4
. The drain of transistor
2
is connected by conductor
6
to a current mirror load circuit including N-channel transistors
4
and
5
, the gates of which are connected to conductor
6
. The sources of transistors
4
and
5
are connected to a low supply voltage V−, and the drain of transistor
5
and the drain of transistor
3
are connected by conductor
7
to an output stage (not shown).
FIG. 1B
shows another conventional CMOS differential amplifier input stage
1
B in which input transistors
2
and
3
are connected as in FIG.
1
A. However, in
FIG. 1B
the drains of input transistors
2
and
3
are connected by conductors
6
and
7
not only to N-channel load transistors
8
and
9
, but also to N-channel cascode transistors
10
and
11
of a folded cascode circuit which also includes current sources
13
and
14
. Specifically, conductor
7
is connected to the drain of load transistor
8
and to the source of cascode transistor
10
, which has its drain connected by conductor
12
to the gates of load transistors
8
and
9
and to one terminal of current source circuit
13
. Conductor
8
is connected to the drain of load transistor
9
and the source of cascode transistor
11
, which has its drain connected to output conductor
15
and to current source circuit
14
.
The voltage gain A of both of differential input stages
1
A and
1
B is given by the expression A=g
m
R
out
, where R
out
is the equivalent differential resistance at the drains of the differential input transistors
2
and
3
. Usually, an output stage (not shown) has a CMOS input transistor the gate of which is connected to the output of the differential input stage
1
A or
1
B. Therefore, R
out
of the differential input stage is dominated by the drain impedances of the transistors connected to output conductor
7
of
FIG. 1A
or output conductor
15
of FIG.
1
B. The voltage gain of the input stage
1
A of FIG.
1
A and the input stage
1
B of
FIG. 1B
typically is roughly 10 to 20, and usually does not exceed 100 (although it is possible for the voltage gain of input stage
1
B of
FIG. 1B
to be as high as 1000, due to the cascode circuitry.)
To achieve higher voltage gain in single stage differential amplifier circuits including folded cascode circuitry such as that shown in
FIGS. 1A and 1B
, gain boost circuits such as those disclosed in above mentioned commonly owned U.S. Pat. Nos. 6,150,883 and 6,356,153 and the above mentioned article by K. Bult and G. Geelan have been provided.
FIG. 2
illustrates such a prior art differential amplifier input stage including such a gain boost circuit
16
, wherein the (+) and (−) inputs of gain boost amplifier
16
are connected to conductors
7
and
6
, respectively. The gate of cascode transistor
11
is connected to the output of gain boost amplifier
16
, instead of to V
BIAS
. If the gain boost amplifier is configured as a voltage-input amplifier in the technique shown in
FIG. 2
, it introduces stability problems and complicates compensation of the amplifier circuit within which the differential amplifier input stage is included. However, if gain boost amplifier
16
is configured as a current-input amplifier to avoid the instability problem, that introduces additional undesirable noise and offset.
It should be understood that one skilled in art who desires to increase the gain of the differential amplifier shown in
FIG. 2
by using the disclosed prior art gain boost technique faces several problems. If he/she wishes to use a voltage-input configuration for the gain boost amplifier
16
, the differential amplifier circuit is likely to be quite unstable and require use of costly and inconvenient compensation circuitry. However, if he/she wishes to use a current-input configuration for the gain boost amplifier
16
, that introduces additional undesirable noise and offset. In either case, some applications require a much larger voltage gain, e.g. greater than 120 dB, in which case a more complex multi-stage amplifier must be designed. Stated differently, differential amplifier shown in prior art
FIG. 2
can provide only 30-40 dB of gain boost, which is not enough gain for many applications, and the noise or instability caused by use of the gain boost circuit
16
may be unacceptable. In such cases, the only available technique for achieving the gain is to provide a multi-stage amplifier, which may be unduly expensive; also, use of multiple amplifying stages slows down overall amplifier performance, requires additional compensation circuitry, and consumes much more current than a single stage amplifier.
Therefore, there is an unmet need for a circuit technique for increasing the open loop gain of a CMOS differential amplifier stage and associated output stage without introducing an unacceptable amount of additional noise, without introducing circuit instability and corresponding compensation problems, and/or without adding additional main gain stages in the signal path.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide an inexpensive, high-speed CMOS amplifier having a gain boost stage which provides substantially increased amplifier gain without introducing of additional noise and which does not cause an unacceptable amount of circuit instability and corresponding compensation problems.
It is another object of the invention to provide an inexpensive, high-speed CMOS amplifier having a gain boost stage which provides substantially increased amplifier gain without introducing additional noise and which does not cause an unacceptable amount of circuit instability and corresponding compensation problems and which renders insignificant any changes in amplifier gain caused by changes in a load driven by the amplifier.
It is another object of the invention to provide circuitry which constitutes a high precision current mirror and which can be used to provide increased gain in a CMOS amplifier.
It is another object of the invention to provide an inexpensive, high-speed CMOS amplifier without using multiple amplifying stages in the signal path.
Briefly described, and in accordance with one embodiment thereof, the invention provides a differential amplifier circuit including differentially connected first and second input transistors of a first channel type and a folded cascode current summing circuit coupled to a first supply voltage rail and including a first cascode transistor and a second cascode transistor both of the second channel type. The sources of the first and second cascode transistors are coupled to drains of the first and second input transistors, respectively. A bias source provides a bias signal on gates of the first and second cascode transistors, respectively. A third cascode transistor of the seco
Ivanov Vadim V.
Meinel Walter B.
Sanchez Stephen J.
Brady W. James
Lam Tuan T.
Nguyen Hiep
Swayze, Jr. W. Daniel
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