Amplifier for use in semiconductor integrated circuits

Details Amplifier for use in semiconductor integrated circuits Amplifier for use in semiconductor integrated circuits

2002-02-04

2004-03-09

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000

Reexamination Certificate

active

06703871

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an amplifier and more particularly, a sense amplifier for a memory device.
2. Background of the Related Art
One of the important factors in the semiconductor field is to operate a device at a high speed. One of the ways to increase the operating speed is to decrease the voltage level of a signal. Since a signal of low voltage level has a small swinging width, the transition of a logic state is fast. Although the voltage level of a signal is lowered to obtain a fast operation speed, the signal needs to be amplified eventually to a magnitude large enough to drive a load, especially when the signal is transferred through a very long signal line. In other words, the voltage level has to be amplified sufficiently.
FIG. 1
shows a schematic of a data output path for semiconductor memory according to a related art. Bit line sense amplifier circuits
104
and
108
of a DRAM in
FIG. 1
amplify a minute voltage difference between each bit line pair BL and /BL connected to memory cell arrays
102
and
106
to data buses DB and /DB. Signals of the data buses DB and /DB are amplified by data bus sense amplifier circuits
110
and
112
and transferred to read data lines RDL and /RDL. The signals of the read data lines are carried to a data output pad through a read data driver and a data output buffer.
As memory capacity increases, so does the area of a memory cell array also increases. Thus, the length of the bit lines or data buses becomes longer. Accordingly, when an output of a bit line sense amplifier is connected directly to a read data line RDL or /RDL, it is hard to expect a fast amplifying operation from the sense amplifier due to the large load on the bit line sense amplifier. Instead, the load on the bit line is alleviated by amplifying the signal which has been amplified by the bit line sense amplifier with a data bus sense amplifier located on the data bus.
The bit line sense amplifier circuit
104
and
108
include a plurality of bit line sense amplifiers, each sense amplifier for a pair of bit lines BL and /BL. The data bus sense amplifier circuit
110
and
112
includes a plurality of sense amplifiers each for a pair of data buses DB and /DB.
FIG. 2
shows a circuit of a current mirror typed sense amplifier used for a semiconductor integrated circuit in a related art. Referring to
FIG. 2
, two PMOS transistors
202
and
204
connected to a power supply voltage VDD are an example of a current mirror typed load
200
. Both gates of the PMOS transistors
202
and
204
are connected to a drain of the PMOS transistor
202
.
Two NMOS transistors
206
and
208
, serving as driving transistors, are connected to the PMOS transistors
202
and
204
, respectively. The NMOS transistor
206
is driven by a data bus signal DB and the NMOS transistor
208
is driven by a data bus bar signal /DB which is a complementary signal of the data bus signal DB. Both of the NMOS transistors
206
and
208
are connected to a current source formed by NMOS transistor
210
, which is activated by a sense amplifier enabling signal SAE.
Each current passing by nodes
212
and
214
is equal to each other because of the current mirror typed load
200
. Thus, the current sinking through the NMOS transistor
210
of the current source to a ground VSS is constant. The current passing through the NMOS transistors
206
and
208
depends on voltage levels of the data bus signal DB and the data bus bar signal /DB, respectively.
When the voltage level of the data bus signal DB is higher than that of the data bus bar signal /DB (even though the difference is very small), drain-source current IDS of the NMOS transistor
206
increases relatively to lower the voltage at the node
212
. On the other hand, drain-source current I
DS
of the NMOS transistor
208
decreases while voltage of the node
214
rises. Accordingly, the voltage difference between a pair of the data bus signals DB and /DB is amplified to a level of the power source voltage VDD.
FIG. 3
shows a circuit of a sense amplifier including two differential amplifiers connected in parallel to generate complementary outputs. A data bus signal DB and a data bar signal /DB are cross-coupled to both a first differential amplifier
420
and a second differential amplifier
422
. The differential amplifiers
420
and
422
produce complementary outputs OUT and /OUT. In the first differential amplifier
420
, a driving NMOS transistor
406
is driven by the data bus signal DB, and a first output OUT is generated from a drain thereof. The other driving NMOS transistor
408
is driven by the data bus bar signal /DB.
In the second differential amplifier
422
, a driving NMOS transistor
418
is driven by the data bus bar signal /DB, and a second output /OUT, which is complementary to the first output OUT, is generated from a drain thereof. The other driving NMOS transistor
416
is driven by the data bus signal DB. The two differential amplifiers are for a single sense amplifier, which provides complementary outputs OUT and /OUT based on complementary data bias signal DB and data bus bar signal /DB.
FIG. 4
shows a circuit of a cross-coupled differential amplifier in a semiconductor integrated circuit which is generally used in a related art as a sense amplifier in semiconductor memory. Referring to
FIG. 4
, two PMOS transistors
602
and
604
are connected to a power supply voltage VDD in parallel and are cross-coupled type loads. Gates of the PMOS transistors
602
and
604
are connected to the drains of reciprocal PMOS transistors
604
and
602
, respectively.
These two PMOS transistors
602
and
604
, as the load, are connected to NMOS transistors
606
and
608
as driving transistors, respectively. The driving NMOS transistor
606
is driven by a data bus signal DB and the driving NMOS transistor
608
is driven by a data bus bar signal /DB. Both of the NMOS transistors
606
are connected to another NMOS transistor
610
which is a current source. The NMOS transistor
610
, which serves as a current source, is activated by a sense amplifier enabling signal SAE.
When the sense amplifier enabling signal SAE is activated to high level, drain-source current I
DS
of the NMOS transistor
606
is larger than the other drain-source current I
DS
of the other NMOS transistor
608
. Therefore, the voltage level of the data bus signal DB which drives the NMOS transistor
606
is higher than the voltage level of the data bus bar signal /DB of the NMOS transistor
608
to the height of the minute voltage difference &Dgr;V, which is very short. Accordingly, the voltage level of the second output /OUT is lower than the voltage level of the first output OUT.
The voltage of the first output OUT rises until a gate-source voltage V
GS
of the PMOS transistor
602
becomes greater than VDD+VTP (a threshold voltage). Then, the PMOS transistor
602
is turned off. Accordingly, the second output /OUT drops down to 0 volt VSS. Once the voltage of the second output /OUT falls down to 0 volt, and the gate-source voltage V
GS
drops under VDD+VTP. Thus, the first output OUT rises up to VDD.
In accordance with such amplification, the minute voltage difference &Dgr;V between the data bus signal DB and the data bus bar signal /DB are amplified to the level of the power supply voltage VDD.
It is the present trend in semiconductor memory to use a lower power supply voltage of 3.3V instead of 5V. Thus, the voltage level of a data bus signal is lower to be closer to the power supply voltage of 3.3V. Accordingly, a sense amplifier using a related current mirror typed differential amplifier is unable to provide a sufficient gain, and its operation speed is unfortunately decreased. In order to make up for these deficiencies, a level shifting is required by which an input voltage level of the differential amplifier is lowered to VDD/2 for maximizing the gain. A level shifter is discussed below for providing amplification at high speed using positive feed-back.
FIG. 5
shows a circu

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