Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
2001-11-19
2003-12-02
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S265000, C330S267000
Reexamination Certificate
active
06657496
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to amplifiers, and more particularly relates to techniques for improving an output drive capability in an output stage of an amplifier without proportionally increasing an input current requirement of the output stage.
BACKGROUND OF THE INVENTION
In certain amplifier or driver applications, such as, for example, in an asymmetric digital subscriber line (ADSL) system, the output current and voltage requirements may be too high for conventional complementary metal-oxide-semiconductor (CMOS) drivers. Consequently, for such applications, bipolar drivers are typically employed. However, in order to meet the speed and/or output drive specifications required by the ADSL system, traditional ADSL drivers designed using bipolar technology generally require an output stage bias current that is large enough to supply a worst case base current to the bipolar output stage transistors. This has traditionally been accomplished by designing the driver to have a quiescent bias current which is large enough to deliver the maximum load current anticipated, which, in a typical ADSL application, may be about 600 milliamperes (mA) or more at a frequency of at least 1 megahertz (MHz).
If the current gain of the output transistors comprising the driver is large (e.g., 100), the input base current required by the driver will be relatively small. However, depending upon semiconductor fabrication process and/or temperature variations, for example, the current gain of the bipolar transistor devices may significantly decrease, and therefore the driver must be designed for such worst case current gain, thus causing the driver to dissipate an undesirable amount of quiescent current under normal operation. For instance, the worst case current gain of a typical npn transistor may be as low as about ten, while the worst case current gain of a pnp transistor can be as low as five. As the current gain of the driver output transistors decreases, the amount of input base current required to deliver the maximum load current must increase proportionally.
Conventional techniques for reducing the quiescent current in an amplifier or driver have been proposed. These techniques, however, are generally not always sufficient or fully effective, and may not be practical, feasible, or otherwise cost-effective to implement in a given application. Accordingly, there exists a need for techniques for increasing an output drive capability of an amplifier without proportionally increasing the amount of input quiescent current required by an output stage of the amplifier.
SUMMARY OF THE INVENTION
The present invention provides techniques for improving an output drive capability in an output stage of an amplifier without proportionally increasing an input quiescent current requirement of the output stage. By utilizing a current regeneration technique, the present invention essentially monitors an input bias current to the output stage and dynamically adjusts the input bias current in response to output load requirements.
In accordance with one aspect of the invention, an amplifier having an improved output current drive capability includes an input stage and an output stage. An input of the output stage is operatively coupled to an output of the input stage. The amplifier further includes a current regeneration circuit operatively coupled to the input of the output stage in a feedback arrangement, the current regeneration circuit feeding back a current to the output circuit in accordance with a predetermined scale factor, the fed back current being proportional to an input current supplied to the output stage. The input current supplied to the output stage is dynamically adjustable by the current regeneration circuit in response to an input current requirement at the output stage.
In accordance with another aspect of the invention, the amplifier includes a slew rate enhancement circuit operatively coupled to the input stage of the amplifier. The slew rate enhancement circuit preferably provides an alternate current path for charging and discharging a compensation circuit included in the amplifier for stabilizing the current regeneration circuit.
REFERENCES:
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patent: 5578967 (1996-11-01), Harvey
patent: 5589798 (1996-12-01), Harvey
patent: 5614866 (1997-03-01), Dow
patent: 6268769 (2001-07-01), Yamauchi et al.
patent: 6429744 (2002-08-01), Murray et al.
Alan B. Grebene, “Bipolar and MOS Analog Integrated Circuit Design,” John Wiley & Sons, pp. 215-246, 1984.
Paul R. Gray et al., “Analysis and Design of Analog Integrated Circuits,” Second Edition, John Wiley & Sons, pp. 233-246, 1984.
Chen Robert Kuo-Wei
Gammel John C.
Havens Joseph H.
Spires Dewayne Alan
Choe Henry
Legerity Inc.
Mendelsohn Steve
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