Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2001-11-08
2003-05-20
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
C330S288000
Reexamination Certificate
active
06566959
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an amplifying circuit, and in particular to an amplifying circuit composed of a basic amplifier and a bias circuit thereof.
In recent years, a MOS semiconductor IC (integrated circuit) technology has remarkably developed, so that the scale of integration and the performance have been improved. This technology is applied to not only a high-performance digital IC but also a high-performance analog IC. For example, an analog-digital hybrid IC by the MOS semiconductor IC technology can realize digital and analog circuits on a single chip by a CMOS process, and is economically advantageous.
In order to apply a CMOS semiconductor IC technology to such a high-performance analog IC, it is important to realize a high-performance analog amplifying circuit using an MOS transistor.
2. Description of the Related Art
FIG. 18
shows an arrangement of a prior art trans-impedance type amplifying circuit
100
, which is composed of an inversion amplifying circuit
10
where three-staged basic amplifiers (hereinafter, occasionally abbreviated as amplifiers)
11
-
13
are connected in cascade, and a feedback resistor R
F
, hereinafter occasionally indicating the resistance value of the resistor R
F
, connecting between an input terminal IN and an output terminal OUT of the inversion amplifying circuit
10
.
The amplifiers
11
-
13
are respectively composed of common-source MOS transistors M
11
, M
21
, and M
31
, and load resistors R
1
, R
2
, and R
3
connected in series to the drains of the MOS transistors M
11
, M
21
, and M
31
.
In the absence of a signal inputted to the input terminal IN, a current does not flow through the feedback resistor R
F
, so that a bias voltage of the amplifying circuit
100
becomes the same as a bias voltage V
0
of the output terminal OUT without any voltage drop being generated at the feedback resistor R
F
.
It is to be noted that the inversion amplifying circuit
10
shown in
FIG. 18
is composed of three basic amplifiers, while an inversion amplifying circuit is generally composed of an odd number of basic amplifiers.
The open loop gain A
1
of the amplifier
11
can be expressed by the following equation (1):
A
1
=g
m1
*R
1
Eq.(1)
where g
m1
is the transconductance of the MOS transistor M
11
, which can be expressed by the following equation (2):
g
m1
=
2
*
μ
N
*
C
OX
*
W
11
L
11
*
I
1
Eq
.
(
2
)
where &mgr;
N
, C
OX
, W
11
, L
11
, and I
1
are respectively the electron mobility, the gate metal oxide capacitance, the channel width, the channel length, and the reference current of the MOS transistor M
11
.
Similarly, the gains A
2
and A
3
of the amplifiers
12
and
13
, and the transconductances g
m2
and g
m3
of the MOS transistors M
21
and M
31
can be respectively expressed by the following equations (3)-(6):
A
2
=g
m2
*R
2
Eq.(3)
A
3
=g
m3
*R
3
Eq.(4)
g
m2
=
2
*
μ
N
*
C
OX
*
W
21
L
21
*
I
2
Eq
.
(
5
)
g
m3
=
2
*
μ
N
*
C
OX
*
W
31
L
31
*
I
3
Eq
.
(
6
)
where W
21
, L
21
, I
2
, and W
31
, L
31
, I
3
are respectively the channel widths, the channel lengths, and the reference currents of the MOS transistors M
21
and M
31
.
The open loop gain A of the inversion amplifying circuit
10
can be expressed by the following equation (7):
A=A
1
*A
2
*A
3
Eq.(7)
Since the transconductances g
m1
-g
m3
vary depending on a process variable condition and a temperature, and the load resistances R
1
-R
3
also vary independently of the transconductances, the gains A
1
, A
2
, and A
3
of the amplifiers
11
-
13
vary extensively.
In case the MOS transistors M
21
and M
31
and the load resistances R
2
and R
3
are respectively the same as the MOS transistor M
11
and the load resistance R
1
for example, the open loop gain A of the inversion amplifying circuit
10
can be expressed by the following equation (8):
A=A
1
3
Eq.(8)
Accordingly, the open loop gain A of the inversion amplifying circuit
10
in this case varies with the cubic of the variation of the gain A
1
.
FIG. 19
shows an arrangement of a general preamplifying circuit for an optical receiver using the amplifying circuit
100
shown in FIG.
18
. This preamplifying circuit is composed of the amplifying circuit
100
, a photo diode PD and an input capacitance C
IN
connected to the input terminal IN of the amplifying circuit
100
. It is to be noted that the input capacitance C
IN
includes the junction capacitance of the photo diode PD and the input capacitance of the inversion amplifying circuit
10
.
In the optical preamplifying circuit, a noise increases when a bandwidth is too wide, while an intersymbol interference caused by a waveform deterioration occurs when the bandwidth is too narrow. Therefore, an allowable range of a cutoff frequency which determines the optimal bandwidth is very narrow. Generally, the optimal range of the cutoff frequency is regarded as 0.6-1.0 times a transmission data rate B.
A close loop bandwidth of the preamplifying circuit will now be obtained. A faint current signal I
IN
from the photo diode PD inputted from the input terminal IN is divided into the input capacitance C
IN
and the feedback resistor R
F
with the values of currents I
C
and I
R
Accordingly, circuit equations of the preamplifying circuit are expressed by the following equations (9)-(12):
I
IN
=I
C
+I
R
Eq.(9)
V
OUT
−V
0
=−A
*(
V
IN
−V
0
) Eq.(10)
V
IN
−V
OUT
=R
F
*I
R
Eq.(11)
V
IN
-
V
0
=
1
j
*
(
2
π
*
f
)
*
C
IN
*
I
C
Eq
.
(
12
)
where f and V
0
are respectively a frequency and the above-mentioned bias voltage.
If I
C
, I
R
, and V
IN
are eliminated from Eqs.(9)-(12) to obtain the relationship between an input current I
IN
and an output voltage V
OUT
, the following equation (13) is held:
V
OUT
=
-
A
1
+
A
+
j
*
(
2
π
*
f
)
*
R
F
*
C
IN
*
R
F
*
I
IN
+
V
0
Eq
.
(
13
)
In case the open loop gain A of the inversion amplifying circuit
10
>>1, the denominator “1” of Eq.(13) can be neglected. Accordingly, a trans-impedance Z
T
assumes the following equation (14) that is Eq.(13) differentiated by the current I
IN
. When the frequency f=0, a trans-impedance Z
T0
assumes the following equation (15), and a bandwidth f
3dB
assumes an equation (16) from (|Z
T
|/Z
T0
|)
2
=½.
Z
T
=
ⅆ
V
OUT
ⅆ
I
IN
=
-
1
1
+
j
*
2
π
*
R
F
*
C
IN
A
*
f
*
R
F
Eq
.
(
14
)
Z
T0
=−R
F
Eq.(15)
f
-
3
dB
=
A
2
π
*
R
F
*
C
IN
Eq
.
(
16
)
In case the open loop gain A>>1, Eq.(16) indicates that the close loop bandwidth of the preamplifying circuit is determined only by the open loop gain A of the inversion amplifying circuit
10
, the input capacitance C
IN
, and the feedback resistance R
F
. For the above-mentioned input capacitance C
IN
and the feedback resistance R
F
, sufficiently stable values can be designed. However, since the open loop gain A in the amplifier of the MOS transistor extensively varies as mentioned above, it is difficult to confine the bandwidth of the preamplifying circuit into the optimal bandwidth, 0.6-1.0 times a transmission data rate B.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide an amplifying circuit comprising a basic amplifier and a bias circuit thereof, and having a gain A stable against variations of process condition and temperature.
As mentioned above, a variation of gain in the amplifying circuit is caused by a transconductance of a transistor generated on a substrate and a load resistance varied with variations of process condition and temperature. Accordingly, if the basic amplifier and the bias circuit can be composed in the form of canceling a variable electron mobility &mgr;
N
, a gate metal oxide capacitance C
OX
, and the like by the process show
Ide Satoshi
Ueno Norio
Fujitsu Limited
Katten Muchin Zavis & Rosenman
Nguyen Khanh Van
Pascal Robert
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